def construct(mod):
c1 = hw.ConstantOp(dim(SIZE), 1)
# CHECK: %[[EQ:.+]] = comb.icmp eq
eq = comb.EqOp(c1, mod.inp)
# CHECK: %[[A1:.+]] = hw.array_create %[[EQ]], %[[EQ]]
a1 = hw.ArrayCreateOp([eq, eq])
# CHECK: %[[A2:.+]] = hw.array_create %[[EQ]], %[[EQ]]
a2 = hw.ArrayCreateOp([eq, eq])
# CHECK: %[[COMBINED:.+]] = hw.array_concat %[[A1]], %[[A2]]
combined = hw.ArrayConcatOp(a1, a2)
mod.out = hw.BitcastOp(dim(SIZE), combined)
def construct(ports):
i32 = types.i32
x = hw.ConstantOp(i32, 23)
poly = PolynomialCompute(Coefficients([62, 42, 6]))("example")
connect(poly.x, x)
PolynomialCompute(coefficients=Coefficients([62, 42, 6]))("example2",
x=poly.y)
PolynomialCompute(Coefficients([1, 2, 3, 4, 5]))("example2", x=poly.y)
cp = CoolPolynomialCompute([4, 42])
cp.x.connect(23)
m = ExternWithParams(8, 3)()
m.name = "pexternInst"
ports.y = poly.y
def construct(mod):
"""Implement this module for input 'x'."""
x = mod.x
taps = list()
for power, coeff in enumerate(coefficients.coeff):
coeffVal = hw.ConstantOp(types.i32, coeff)
if power == 0:
newPartialSum = coeffVal
else:
partialSum = taps[-1]
if power == 1:
currPow = x
else:
x_power = [x for i in range(power)]
currPow = comb.MulOp(*x_power)
newPartialSum = comb.AddOp(partialSum,
comb.MulOp(coeffVal, currPow))
taps.append(newPartialSum)
# Final output
mod.y = taps[-1]
def build(ports):
# a 32x32xi1 ndarray.
# A dtype of i32 is fairly expensive wrt. the size of the output IR, but
# but allows for assigning indiviudal bits.
m = NDArray((32, 32), dtype=types.i1, name='m1')
# Assign individual bits to the first 32 bits.
for i in range(32):
m[0, i] = hw.ConstantOp(types.i1, 1)
# Fill the next 15 values with an i32. The ndarray knows how to convert
# from i32 to <32xi1> to comply with the ndarray dtype.
for i in range(1, 16):
m[i] = ports.in1
# Fill the upportmost 16 rows with the input array of in0 : 16xi32
m[16:32] = ports.in0
# We don't provide a method of reshaping the ndarray wrt. its dtype.
# that is: 32x32xi1 => 32xi32
# This has massive overhead in the generated IR, and can be easily
# achieved by a bitcast.
ports.c = hw.BitcastOp(M5.t_c, m.to_circt())
def _get_constant(self, value: int, width: int = 32):
""" Get an IR constant backed by a constant cache."""
return hw.ConstantOp(ir.IntegerType.get_signless(width), value)