def build(_): types.struct({"foo": types.i12})({"foo": 7}) dim(types.i8, 2)([42, 45]) types.i8(5) BarType({"foo": 7}) Taps() StupidLegacy(ignore=no_connect)
def construct(mod): c1 = hw.ConstantOp(dim(SIZE), 1) # CHECK: %[[EQ:.+]] = comb.icmp eq eq = comb.EqOp(c1, mod.inp) # CHECK: %[[A1:.+]] = hw.array_create %[[EQ]], %[[EQ]] a1 = hw.ArrayCreateOp([eq, eq]) # CHECK: %[[A2:.+]] = hw.array_create %[[EQ]], %[[EQ]] a2 = hw.ArrayCreateOp([eq, eq]) # CHECK: %[[COMBINED:.+]] = hw.array_concat %[[A1]], %[[A2]] combined = hw.ArrayConcatOp(a1, a2) mod.out = hw.BitcastOp(dim(SIZE), combined)
class Slicing: In = Input(dim(8, 4, 5)) Sel8 = Input(types.i8) Sel2 = Input(types.i2) OutIntSlice = Output(types.i2) OutArrSlice8 = Output(dim(8, 4, 2)) OutArrSlice2 = Output(dim(8, 4, 2)) @generator def create(ports): i = ports.In[0][0] ports.OutIntSlice = i.slice(ports.Sel2, 2) ports.OutArrSlice2 = ports.In.slice(ports.Sel2, 2) ports.OutArrSlice8 = ports.In.slice(ports.Sel8, 2)
def build(ports): foo = ports.data_in[0] foo.name = "foo" arr_data = dim(32, 4)([1, 2, 3, 4], "arr_data") ports.set_all_ports({ 'a': foo.reg(ports.clk).reg(ports.clk), 'b': arr_data[ports.sel], })
class Mux: clk = Clock() data = Input(dim(8, 14)) sel = Input(types.i4) out = Output(types.i8) @generator def build(ports): sel_reg = ports.sel.reg() ports.out = ports.data.reg()[sel_reg].reg()
class WireNames: clk = Input(types.i1) sel = Input(types.i2) data_in = Input(dim(32, 3)) a = Output(types.i32) b = Output(types.i32) @generator def build(ports): foo = ports.data_in[0] foo.name = "foo" arr_data = dim(32, 4)([1, 2, 3, 4], "arr_data") ports.set_all_ports({ 'a': foo.reg(ports.clk).reg(ports.clk), 'b': arr_data[ports.sel], })
class ComplexPorts: clk = Input(types.i1) sel = Input(types.i2) data_in = Input(dim(32, 3)) struct_data_in = Input(types.struct({"foo": types.i36})) a = Output(types.i32) b = Output(types.i32) c = Output(types.i32) @generator def build(ports): assert len(ports.data_in) == 3 ports.set_all_ports({ 'a': ports.data_in[0].reg(ports.clk).reg(ports.clk), 'b': ports.data_in[ports.sel], 'c': ports.struct_data_in.foo[:-4] })
class ComplexMux: Clk = Input(dim(1)) In = Input(dim(3, 4, 5)) Sel = Input(dim(1)) Out = Output(dim(3, 4)) OutArr = Output(dim(3, 4, 2)) OutSlice = Output(dim(3, 4, 3)) OutInt = Output(types.i1) @generator def create(ports): clk = ports.Clk select_from = Value([ports.In[3].reg(clk).reg(clk, cycles=2), ports.In[1]]) ports.Out = select_from[ports.Sel] ports.OutArr = array_from_tuple(ports.In[0], ports.In[1]) ports.OutSlice = ports.In[0:3] ports.OutInt = ports.In[0][0][ports.Sel]
class Taps: taps = Output(dim(8, 3)) @generator def build(ports): ports.taps = [203, 100, 23]
class StupidLegacy: ignore = Input(dim(1, 4))
# RUN: %PYTHON% %s 2>err.txt | FileCheck %s # RUN: cat err.txt | FileCheck --check-prefix=ERR %s from pycde import dim, types # CHECK: [('foo', Type(i1)), ('bar', Type(i13))] # ERR: i1 st1 = types.struct({"foo": types.i1, "bar": types.i13}) print(st1.fields) st1.foo.dump() print() from mlir.ir import Module # ERR: i6 array1 = dim(types.i6) array1.dump() print() # CHECK: i6 print(array1) # ERR: !hw.array<12xarray<10xi6>> array2 = dim(6, 10, 12) array2.dump() print() # CHECK: [12][10]i6 print(array2) # ERR: !hw.typealias<@pycde::@myname1, i8> int_alias = types.int(8, "myname1") int_alias.dump()