def test_socket_cosim_rand():
skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST')
din_num = 3
cons = []
for i in range(din_num):
cons.append(randomize(T_DIN, f'din{i}', eot_cons=['data_size == 10']))
stim = []
for i in range(din_num):
stim.append(drv(t=T_DIN, seq=rand_seq(f'din{i}', 30)))
verif(*stim,
f=qinterlace(sim_cls=partial(SimSocket, run=True)),
ref=qinterlace(name='ref_model'))
sim(extens=[partial(SVRandSocket, cons=cons)])
def test_random(sim_cls):
skip_ifndef('RANDOM_TEST')
din_num = 3
stim = []
for _ in range(din_num):
stim.append(
drv(t=T_DIN,
seq=[
list(range(random.randint(1, 10))),
list(range(random.randint(1, 10)))
]))
verif(*stim,
f=qinterlace(sim_cls=sim_cls),
ref=qinterlace(name='ref_model'))
sim()
def test_trr_vivado():
qinterlace(Intf(T_DIN), Intf(T_DIN), Intf(T_DIN))
def test_formal():
qinterlace(Intf(T_DIN), Intf(T_DIN), Intf(T_DIN))
def test_trr_yosys():
qinterlace(Intf(T_DIN), Intf(T_DIN), Intf(T_DIN))
