def test_hier_level2(lang):
reg['gear/memoize'] = True
@gear
def test(a, b):
return a + b
@gear
def test_hier(a, b, c, d):
return test(a, b) + test(c, d)
@gear
def top(a, b, c, d):
return test_hier(a, b, c, d) + test_hier(a, b, c, d)
directed(drv(t=Uint[4], seq=[1]),
drv(t=Uint[4], seq=[2]),
drv(t=Uint[4], seq=[3]),
drv(t=Uint[4], seq=[4]),
f=top,
ref=[20])
assert check_memoized('/top/test_hier1', '/top/test_hier0/test1')
cosim('/top', 'verilator', lang=lang)
sim()
def test_directed(tmpdir, do_cosim):
pw = 19
iw = 12
ow = 12
pi = 2**pw / 2
phase_seq = [
0, pi / 6, pi / 4, pi / 3, pi / 2, 2 * pi / 3, 3 * pi / 4, 5 * pi / 6,
pi, 7 * pi / 6, 5 * pi / 4, 4 * pi / 3, 3 * pi / 2, 5 * pi / 3,
7 * pi / 4, 11 * pi / 6, (2 * pi) - 1
]
ref_seq_sin = [
0, 596, 843, 1032, 1192, 1032, 843, 596, 0, -596, -842, -1032, -1192,
-1032, -843, -596, 0
]
ref_seq_cos = [
1192, 1032, 843, 596, 0, -596, -843, -1032, -1192, -1032, -843, -596,
0, 596, 842, 1032, 1192
]
directed(drv(t=Uint[pw], seq=phase_seq),
f=cordic_sin_cos(ow=ow,
iw=iw,
norm_gain_sin=False,
norm_gain_cos=False,
name='dut'),
ref=[ref_seq_sin, ref_seq_cos])
if do_cosim:
cosim('/dut', 'verilator')
# sim(outdir='/tools/home/tmp/verilator')
sim(tmpdir, timeout=100)
def test_async_over_if_over_async_over_if(lang, din_delay, dout_delay):
@gear
async def test(sel: Bool, din0: Uint,
din1: Uint) -> b'max(din0, din1) * Uint[2]':
async with sel as s:
if s:
async with din1 as d1:
if d1 > 4:
yield d1
else:
async with din0 as d0:
if d0 < 2:
yield d0
elif d0 > 0:
yield d0 * 2
directed(drv(t=Bool, seq=[0, 1, 0, 1, 0, 1, 0, 1]),
drv(t=Uint[4], seq=list(range(4)))
| delay_rng(din_delay, din_delay),
drv(t=Uint[4], seq=list(range(4, 8)))
| delay_rng(din_delay, din_delay),
f=test,
ref=[0, 1, 5, 4, 6, 6, 7])
cosim('/test', 'verilator', lang=lang)
sim(check_activity=False)
def test_hold(lang):
@gear
async def wr_sequence() -> Uint[4]:
for i in range(4):
yield i + 1
await clk()
await clk()
await clk()
raise GearDone
@gear
async def rd_sequence() -> Unit:
for i in range(4):
yield Unit()
await clk()
await clk()
raise GearDone
directed(wr_sequence(),
rd_sequence(),
f=state(hold=True),
ref=[0, 2, 3, 4],
delays=[delay(2)])
cosim('/state', 'verilator', lang=lang)
sim()
def test_sample(sim_cls):
directed(
drv(t=Uint[2], seq=[1, 2]) | delay(2),
f=sample(sim_cls=sim_cls),
ref=[1, 1, 1, 2])
sim(timeout=7)
def test_list_to_array_2d(cosim_cls):
@gear
async def test() -> Array[Array[Uint[4], 2], 2]:
yield [[0] * 2] * 2
directed(f=test(sim_cls=cosim_cls), ref=[[[0] * 2] * 2] * 2)
sim(timeout=2)
def test_lvl1(cosim_cls):
directed(drv(t=Queue[Uint[4]], seq=[list(range(4)),
list(range(4))]),
f=sot_queue(sim_cls=cosim_cls),
ref=[(0, 1), (1, 0), (2, 0), (3, 0), (0, 1), (1, 0), (2, 0),
(3, 0)])
sim()
def test_simple_async_sim(sim_cls):
@gear(hdl={'compile': True})
async def test() -> Uint[3]:
async for i, _ in qrange(4):
yield i
directed(f=test(sim_cls=sim_cls), ref=list(range(4)) * 2)
sim(timeout=8)
def test_two_alter_outs_const():
@gear
async def test() -> (Uint[4], Uint[4]):
yield 0, None
yield None, 1
directed(f=test(__sim__='verilator'), ref=[[0, 0], [1, 1]])
sim(timeout=4)
def test_simple_async_sim(sim_cls):
@gear
async def test() -> Uint[3]:
async for i, _ in qrange(4):
yield i
directed(f=test(sim_cls=sim_cls), ref=list(range(4)) * 4)
sim(timeout=4 * 4)
def test_lvl3(cosim_cls):
from pygears.lib import sot_queue, directed
directed(drv(t=Queue[Uint[4], 3],
seq=[[[[0, 1], [2, 3]], [[4, 5], [6, 7]]]]),
f=sot_queue(sim_cls=cosim_cls),
ref=[(0, 7), (1, 6), (2, 5), (3, 4), (4, 3), (5, 2), (6, 1),
(7, 0)])
sim()
def test_unit_const():
@gear
async def test() -> Queue[Unit]:
yield Unit(), Bool(False)
yield Unit(), Bool(True)
directed(f=test(__sim__='verilator'), ref=[[Unit(), Unit()]])
sim(timeout=2)
def test_yield_var():
@gear
async def test(din: Uint[2]) -> Uint[2]:
yield din
directed(drv(t=Uint[2], seq=list(range(3)) * 3),
f=test(__sim__='verilator'),
ref=[0, 1, 2] * 3)
sim(timeout=3 * 3)
def test_saturate_uint(sim_cls):
seq = [0, 14, 15, 16, 32, 63]
ref = [0, 14, 15, 15, 15, 15]
directed(drv(t=Uint[6], seq=seq),
f=saturate(t=Uint[4], sim_cls=sim_cls),
ref=ref)
sim()
def test_saturate_int_to_larger(sim_cls):
seq = [-63, -32, -17, -16, 0, 14, 15, 16, 32, 63]
ref = seq
directed(drv(t=Int[7], seq=seq),
f=saturate(t=Int[9], sim_cls=sim_cls),
ref=ref)
sim()
def test_saturate_ufixp(sim_cls):
dtype = Ufixp[4, 8]
sat_type = Ufixp[2, 6]
seq = [0.0, sat_type.fmax, sat_type.fmax + dtype.quant, dtype.fmax]
ref = [0.0, sat_type.fmax, sat_type.fmax, sat_type.fmax]
directed(drv(t=dtype, seq=seq), f=saturate(t=sat_type), ref=ref)
sim()
def test_directed(sim_cls, din_delay, dout_delay):
dut = get_dut(dout_delay)
directed(drv(t=t_din, seq=[list(range(9)), list(range(3))])
| delay_rng(din_delay, din_delay),
drv(t=t_cfg, seq=[2, 3]) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=[[0, 1], [2, 3], [4, 5], [6, 7], [8], [0, 1, 2]],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_saturate_int(sim_cls):
seq = [-63, -32, -17, -16, 0, 14, 15, 16, 32, 63]
ref = [-16, -16, -16, -16, 0, 14, 15, 15, 15, 15]
directed(drv(t=Int[7], seq=seq),
f=saturate(t=Int[5], sim_cls=sim_cls),
ref=ref)
sim()
def test_inline_if(cosim_cls):
@gear
async def inv(din: Bool) -> Bool:
async with din as data:
yield 0 if data else 1
directed(drv(t=Bool, seq=[1, 0]), f=inv(sim_cls=cosim_cls), ref=[0, 1])
sim()
def test_simple(sim_cls):
@gear
async def test() -> Uint[3]:
for i in range(4):
yield i
directed(f=test(sim_cls=sim_cls), ref=list(range(4)) * 2)
sim(timeout=8)
def test_simple_qrange(sim_cls):
@gear
async def test() -> Queue[Uint[3]]:
for i, last in qrange(4):
yield i, last
directed(f=test(sim_cls=sim_cls), ref=[list(range(4))] * 2)
sim(timeout=8)
def test_const_op():
@gear
async def test() -> Uint[3]:
yield 1 + 1
yield 2 + 2
yield 3 + 3
directed(f=test(__sim__='verilator'), ref=[2, 4, 6])
sim(timeout=3)
def test_basic(tmpdir, sim_cls):
tin = Tuple['a':Uint[1], 'b':Uint[2], 'c':Uint[3], 'd':Uint[4]]
tout = Tuple['a':Uint[1], 'c':Uint[3]]
directed(drv(t=tin, seq=[(1, 2, 3, 4)] * 3),
f=repack(t=tout, sim_cls=sim_cls),
ref=[(1, 3)] * 3)
sim(tmpdir)
def test_basic():
@gear
def qrange_wrp(din):
return qrange(din)
directed(drv(t=Uint[4], seq=[4]), f=qrange_wrp, ref=[list(range(4))])
find('/qrange_wrp/qrange').meta_kwds['hdl']['lang'] = 'v'
cosim('/qrange_wrp', 'verilator', lang='sv')
sim()
def accum_test(accum_gear, reduce_func):
init = [7, 45]
seq = [list(range(0, 100, 10)), list(range(2))]
directed(drv(t=Queue[Uint[8]], seq=seq),
drv(t=Uint[8], seq=init),
f=accum_gear,
ref=[freduce(reduce_func, s, i) for s, i in zip(seq, init)])
sim()
def test_simple(sim_cls):
@gear(hdl={'compile': True})
async def test(din: Queue) -> b'din':
async for (data, eot) in din:
yield data, eot
directed(drv(t=Queue[Uint[4]], seq=[list(range(10))]),
f=test(sim_cls=sim_cls),
ref=[list(range(10))])
sim()
def test_expr_index(cosim_cls):
@gear
async def test(din: Tuple[Uint[4], Uint[3]]) -> Bool:
async with din as (data, i):
yield (data @ data)[i]
directed(drv(t=Tuple[Uint[4], Uint[3]], seq=[(0xa, i) for i in range(8)]),
f=test(sim_cls=cosim_cls),
ref=[0, 1, 0, 1, 0, 1, 0, 1])
sim()
def test_type_int(sim_cls):
@gear
async def test(din: Integer['w'], *, t) -> b't':
async with din as d:
yield dispatch_types(t, d)
directed(drv(t=Uint[8], seq=[0, 1, 2]),
f=test(sim_cls=sim_cls, t=Int[16]),
ref=[-1, 0, 1])
sim(timeout=3)
def test_unit():
@gear
async def test(din) -> Queue[Unit]:
async for d, eot in din:
yield Unit(), eot
directed(drv(t=Queue[Uint[4]], seq=[[1, 2]]),
f=test(__sim__='verilator'),
ref=[[Unit(), Unit()]])
sim(timeout=2)
def test_simple_int(sim_cls):
@gear
async def test(din: Integer['w']) -> b'din.base[w+1]':
async with din as d:
yield dispatch_test(d)
directed(drv(t=Int[8], seq=[0, -1, -2]),
f=test(sim_cls=sim_cls),
ref=[-1, -2, -3])
sim(timeout=3)
