def test_async_over_if_over_async_over_if(lang, din_delay, dout_delay):
@gear
async def test(sel: Bool, din0: Uint,
din1: Uint) -> b'max(din0, din1) * Uint[2]':
async with sel as s:
if s:
async with din1 as d1:
if d1 > 4:
yield d1
else:
async with din0 as d0:
if d0 < 2:
yield d0
elif d0 > 0:
yield d0 * 2
directed(drv(t=Bool, seq=[0, 1, 0, 1, 0, 1, 0, 1]),
drv(t=Uint[4], seq=list(range(4)))
| delay_rng(din_delay, din_delay),
drv(t=Uint[4], seq=list(range(4, 8)))
| delay_rng(din_delay, din_delay),
f=test,
ref=[0, 1, 5, 4, 6, 6, 7])
cosim('/test', 'verilator', lang=lang)
sim(check_activity=False)
def test_qround_non_default():
verif(drv(t=Fixp[11, 33], seq=[1, 2, 117]),
f=qround(name='dut', fract=21),
ref=qround(fract=21))
cosim('/dut', 'verilator', outdir='/tmp/qround')
sim()
def test_code_unit_to_unit(lang):
verif(drv(t=Uint[0], seq=[0, 0]),
f=code_gear(name='dut', t=Unit),
ref=code_gear(t=Unit))
cosim('/dut', 'verilator', lang=lang)
sim()
def test_code_unit(lang):
verif(drv(t=Uint[1], seq=list(range(2))),
f=code_gear(name='dut', t=Unit),
ref=code_gear(t=Unit))
cosim('/dut', 'verilator', lang=lang)
sim()
def test_hier_level2(lang):
reg['gear/memoize'] = True
@gear
def test(a, b):
return a + b
@gear
def test_hier(a, b, c, d):
return test(a, b) + test(c, d)
@gear
def top(a, b, c, d):
return test_hier(a, b, c, d) + test_hier(a, b, c, d)
directed(drv(t=Uint[4], seq=[1]),
drv(t=Uint[4], seq=[2]),
drv(t=Uint[4], seq=[3]),
drv(t=Uint[4], seq=[4]),
f=top,
ref=[20])
assert check_memoized('/top/test_hier1', '/top/test_hier0/test1')
cosim('/top', 'verilator', lang=lang)
sim()
def test_cast_union_of_units(lang):
verif(drv(t=Tuple[Unit, Uint[1]], seq=[(Unit(), 0), (Unit(), 1)]),
f=cast(name='dut', t=Union[Unit, Unit]),
ref=code_gear(t=Union[Unit, Unit]))
cosim('/dut', 'verilator', lang=lang)
sim()
def test_directed(tmpdir, do_cosim):
pw = 19
iw = 12
ow = 12
pi = 2**pw / 2
phase_seq = [
0, pi / 6, pi / 4, pi / 3, pi / 2, 2 * pi / 3, 3 * pi / 4, 5 * pi / 6,
pi, 7 * pi / 6, 5 * pi / 4, 4 * pi / 3, 3 * pi / 2, 5 * pi / 3,
7 * pi / 4, 11 * pi / 6, (2 * pi) - 1
]
ref_seq_sin = [
0, 596, 843, 1032, 1192, 1032, 843, 596, 0, -596, -842, -1032, -1192,
-1032, -843, -596, 0
]
ref_seq_cos = [
1192, 1032, 843, 596, 0, -596, -843, -1032, -1192, -1032, -843, -596,
0, 596, 842, 1032, 1192
]
directed(drv(t=Uint[pw], seq=phase_seq),
f=cordic_sin_cos(ow=ow,
iw=iw,
norm_gain_sin=False,
norm_gain_cos=False,
name='dut'),
ref=[ref_seq_sin, ref_seq_cos])
if do_cosim:
cosim('/dut', 'verilator')
# sim(outdir='/tools/home/tmp/verilator')
sim(tmpdir, timeout=100)
def test_double_loop(din_delay, dout_delay):
@gear
async def test(stop: Integer) -> b'stop + stop':
cnt1 = stop.dtype(0)
async with stop as s:
last1 = False
while not last1:
cnt2 = stop.dtype(0)
last2 = False
while not last2:
yield cnt1 + cnt2
last2 = cnt2 == s
cnt2 += 1
last1 = cnt1 == s
cnt1 += 1
verif(drv(t=Uint[4], seq=[2, 4]) | delay_rng(din_delay, din_delay),
f=test(name='dut'),
ref=test,
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim()
def test_complex(din_delay, dout_delay):
@gear
async def test(din, *, chunk_len, num_workers) -> b'din':
counter = Uint[bitw(chunk_len * chunk_len)](0)
chunk_pow = chunk_len * chunk_len
async for arr, last_arr in din:
if counter >= chunk_pow:
counter = 0
if not last_arr:
yield arr, last_arr
counter += 1
if last_arr:
if counter == chunk_pow - 1:
yield arr, last_arr
else:
yield arr, Uint[1](0)
counter += 1
while counter < chunk_pow - 1 and last_arr:
yield [[0] * chunk_len] * num_workers, Uint[1](0)
counter += 1
yield [[0] * chunk_len] * num_workers, Uint[1](1)
t = Queue[Array[Array[Uint[4], 2], 2]]
verif(drv(t=t, seq=[[((1, 2),
(2, 3))] * 5]) | delay_rng(din_delay, din_delay),
f=test(name='dut', chunk_len=2, num_workers=2),
ref=test(chunk_len=2, num_workers=2),
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim()
def test_cond_nested_loop(din_delay, dout_delay):
@gear
async def test(din: Queue[Bool]) -> Uint[4]:
a = Uint[4](0)
i = Uint[4](0)
while i < 4:
if i < 2:
async for d in din:
print(f'1: {a}')
yield a
a += 1
i = 2
else:
async for d in din:
print(f'2: {a}')
yield a
a += 2
i = 4
i += 1
verif(drv(t=Queue[Bool], seq=[[True] * 4, [True], [True], [True] * 4])
| delay_rng(din_delay, din_delay),
f=test(name='dut'),
ref=test,
delays=[delay_rng(dout_delay, dout_delay)])
# cosim('/dut', 'verilator', outdir='/tools/home/tmp/shedule', rebuild=True)
cosim('/dut', 'verilator')
sim()
def test_hold(lang):
@gear
async def wr_sequence() -> Uint[4]:
for i in range(4):
yield i + 1
await clk()
await clk()
await clk()
raise GearDone
@gear
async def rd_sequence() -> Unit:
for i in range(4):
yield Unit()
await clk()
await clk()
raise GearDone
directed(wr_sequence(),
rd_sequence(),
f=state(hold=True),
ref=[0, 2, 3, 4],
delays=[delay(2)])
cosim('/state', 'verilator', lang=lang)
sim()
def test_sim_invoke(lang):
@gear(hdl={'compile': True})
async def sat_wrap(din) -> b'din':
async with din as d:
saturate.exec(d, t=Uint[8])
drv(t=Uint[8], seq=[7]) | sat_wrap | shred
cosim('/sat_wrap', 'verilator', lang=lang)
sim()
def test_cosim():
seq = list(range(1, 10))
directed(drv(t=Uint[16], seq=seq) | delay_rng(0, 2),
f=viv_fifo(depth=16),
ref=seq,
delays=[delay_rng(0, 2)])
cosim('/viv_fifo', 'xsim')
sim()
def test_qround_fixp(lang):
seq = [
-1.5 - 0.0625, -1.5, -0.5 - 0.0625, -0.5, 0.5 - 0.0625, 0.5,
1.5 - 0.0625, 1.5
]
verif(drv(t=Fixp[6, 10], seq=seq), f=qround(name='dut'), ref=qround)
cosim('/dut', 'verilator', lang=lang)
sim()
def test_basic():
@gear
def qrange_wrp(din):
return qrange(din)
directed(drv(t=Uint[4], seq=[4]), f=qrange_wrp, ref=[list(range(4))])
find('/qrange_wrp/qrange').meta_kwds['hdl']['lang'] = 'v'
cosim('/qrange_wrp', 'verilator', lang='sv')
sim()
def test_2state(dout_delay):
@gear
async def test() -> Bool:
yield False
yield True
verif(f=test(name='dut'),
ref=test(),
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim(timeout=8)
def test_directed(latency):
print(f'Latency: {latency}')
wr_addr_data = [(i, i * 2) for i in range(4)]
rd_addr = list(range(4))
rd_data = [i * 2 for i in range(4)]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=wr_addr_data),
drv(t=Uint[3], seq=rd_addr) | delay_rng(latency, latency),
f=sdp(depth=4, latency=latency),
ref=rd_data)
cosim('/sdp', 'verilator')
sim()
def test_unfold(lang):
@gear
async def test() -> Array[Uint[3], 4]:
data = Array[Uint[3], 4]()
for i in range(4):
data[i] = i
yield data
directed(f=test(), ref=[(0, 1, 2, 3)] * 2)
cosim('/test', 'verilator', lang=lang)
sim(timeout=2)
def test_while_loop_reg_infer(lang):
@gear
async def test() -> Uint[32]:
cnt = Uint[10](0)
while cnt != 10:
yield cnt
cnt += 1
directed(f=test(), ref=list(range(10)) * 3)
cosim('/test', 'verilator', lang=lang)
sim(timeout=30)
def test_code(lang):
@datagear
def test(din, *, t) -> b't':
return code(din, t)
cast_t = Maybe[Uint[31]]
verif(drv(t=Uint[32], seq=list(range(10))),
f=test(name='dut', t=cast_t),
ref=test(t=cast_t))
cosim('/dut', 'verilator', lang=lang)
sim()
def test_bare(lang, din_delay, dout_delay):
@gear
async def test(din: Uint) -> b'din':
async with din as d:
yield d
directed(drv(t=Uint[4], seq=list(range(4)))
| delay_rng(din_delay, din_delay),
f=test,
ref=list(range(4)))
cosim('/test', 'verilator', lang=lang)
sim(check_activity=False)
def test_unpack(lang):
@gear
async def test(din: Tuple) -> b'din[0] + din[1]':
async with din as (d1, d2):
yield d1 + d2
directed(drv(t=Tuple[Uint[4], Uint[4]],
seq=[(i, i + 4) for i in range(4)]),
f=test,
ref=[2 * i + 4 for i in range(4)])
cosim('/test', 'verilator', lang=lang)
sim(check_activity=False)
def test_cordic_stage(tmpdir, do_cosim):
verif(drv(t=Tuple[Int[15], Int[15], Uint[19]],
seq=[(-4768, 1768, 0xbaba)]),
f=cordic_stage(i=1,
ww=15,
pw=20,
cordic_angle=Uint[20](0xbaba),
name='dut'),
ref=cordic_stage(i=1, ww=15, pw=20, cordic_angle=Uint[20](0xbaba)))
if do_cosim:
cosim('/dut', 'verilator')
sim(tmpdir)
def test_unfold_uint(lang):
@gear
async def test(din: Bool, *, w_dout) -> Uint['w_dout']:
data = Array[Bool, w_dout](None)
async with din as d:
for i in range(w_dout):
data[i] = d
yield code(data, Uint)
directed(drv(t=Bool, seq=[0, 1]), f=test(w_dout=8), ref=[0x00, 0xff])
cosim('/test', 'verilator', lang=lang)
sim(timeout=2)
def test_loop_select_intfs(lang):
@gear
async def test(*din: Uint) -> b'din[0]':
dsel: Uint[4]
for i in range(len(din)):
async with select(i, *din) as d:
yield d
directed(drv(t=Uint[4], seq=list(range(4))),
drv(t=Uint[4], seq=list(range(4, 8))),
f=test,
ref=[0, 4, 1, 5, 2, 6, 3, 7])
cosim('/test', 'verilator', lang=lang)
sim(check_activity=False)
def test_enum_intfs_single(lang, din_delay, dout_delay):
@gear
async def test(*din: Uint) -> b'din[0]':
for i, d in enumerate(din):
async with d as data:
yield data
directed(drv(t=Uint[4], seq=list(range(4)))
| delay_rng(din_delay, din_delay),
f=test,
delays=[delay_rng(dout_delay, dout_delay)],
ref=list(range(4)))
cosim('/test', 'verilator', lang=lang)
sim(check_activity=False)
def test_state_in_scope(din_delay, dout_delay):
@gear
async def test(din: Queue[Uint[4]]) -> Uint[4]:
async for c, eot in din:
yield c
yield c
verif(drv(t=Queue[Uint[4]], seq=[[2, 6, 10, 14]])
| delay_rng(din_delay, din_delay),
f=test(name='dut'),
ref=test,
delays=[delay_rng(dout_delay, dout_delay)])
cosim('/dut', 'verilator')
sim()
def test_directed_full_read(latency):
print(f'Latency: {latency}')
depth = 8
mem = list(range(depth))
rd_addr = list(range(8))
rd_data = list(range(8))
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=[]),
drv(t=Uint[3], seq=rd_addr),
f=sdp(depth=8, latency=latency, mem=mem),
ref=rd_data)
cosim('/sdp', 'verilator')
sim()
def test_regmap(lang):
t_addr = Uint[2]
t_data = Uint[8]
directed(drv(t=Tuple[t_addr, t_data], seq=[(0, 0), (3, 1), (0, 2),
(0, 3)]),
f=regmap(addrmap={
0: 0,
3: 1
}, initmap={1: 9}),
ref=[[0, 0, 2, 3, 3], [9, 9, 1, 1, 1, 1]])
cosim('/regmap', 'verilator', lang=lang)
sim(timeout=6)
def test_cond_no_state(lang):
@gear
async def test(din: Bool) -> Bool:
async with din as d:
if d:
yield True
else:
yield False
directed(drv(t=Bool, seq=[True, False, True, False]),
f=test,
ref=[True, False, True, False])
cosim('/test', 'verilator', lang=lang)
sim(timeout=4)
