def test_get_address(self): """ Tests getting the full 6-bit L1 address a synapse decodes """ import pyhalbe import pysthal from pyhalco_common import Enum, top, bottom import pyhalco_hicann_v2 as C h = pysthal.HICANN() for syn_c in C.iter_all(C.SynapseOnHICANN): drv_c = syn_c.toSynapseDriverOnHICANN() row_config_c = syn_c.toSynapseRowOnHICANN().toRowOnSynapseDriver() syn = h.synapses[syn_c] drv = h.synapses[drv_c] row_config = drv[row_config_c] for addr in C.iter_all(pyhalbe.HICANN.L1Address): syn.decoder = addr.getSynapseDecoderMask() row_config.set_decoder( top if syn_c.toSynapseColumnOnHICANN().toEnum().value() % 2 == 0 else bottom, addr.getDriverDecoderMask()) self.assertEqual(addr, h.synapses.get_address(syn_c))
def set_floating_gate_to_zero(hicann): """Set all floating gate values to zero""" fgc = hicann.floating_gates for block in C.iter_all(C.FGBlockOnHICANN): blk = fgc[block] for cell in C.iter_all(C.FGCellOnFGBlock): blk.setRaw(cell, 0)
def reset_hicann_config(self): """ Set hicann configuration to default values, with zeroed floating gates """ for hicann_c in self.hicanns: hicann = self.wafer[hicann_c] hicann.clear() for block in Coordinate.iter_all(Coordinate.FGBlockOnHICANN): fgblock = hicann.floating_gates[block] for cell in Coordinate.iter_all(Coordinate.FGCellOnFGBlock): fgblock.setRaw(cell, 0)
def test_save_and_load(self): import pysthal from pyhalco_common import Enum import pyhalco_hicann_v2 as Coordinate from pyhalbe import HICANN wafer = pysthal.Wafer(Coordinate.Wafer(3)) hicann1 = wafer[Coordinate.HICANNOnWafer(Enum(30))] for row in Coordinate.iter_all(Coordinate.SynapseRowOnHICANN): d_pattern = numpy.random.randint(0, 16, 256) d_pattern[d_pattern[0] + 23] = 15 hicann1.synapses[row].decoders[:] = [ HICANN.SynapseDecoder(int(ii)) for ii in d_pattern ] w_pattern = numpy.random.randint(0, 16, 256) w_pattern[w_pattern[0] + 23] = 15 hicann1.synapses[row].weights[:] = [ HICANN.SynapseWeight(int(ii)) for ii in w_pattern ] wafer2 = pysthal.Wafer(Coordinate.Wafer(0)) hicann2 = wafer2[Coordinate.HICANNOnWafer(Enum(42))] self.assertNotEqual(str(wafer.status()), str(wafer2.status())) for row in Coordinate.iter_all(Coordinate.SynapseRowOnHICANN): d1 = hicann1.synapses[row].decoders d2 = hicann2.synapses[row].decoders self.assertNotEqual(d1, d2) w1 = hicann1.synapses[row].weights w2 = hicann2.synapses[row].weights self.assertNotEqual(w1, w2) with tempfile.NamedTemporaryFile() as f: wafer.dump(f.name, True) wafer2.load(f.name) self.assertEqual(wafer.size(), wafer2.size()) hicann1 = wafer[Coordinate.HICANNOnWafer(Enum(30))] hicann2 = wafer2[Coordinate.HICANNOnWafer(Enum(30))] self.assertEqual(hicann1.index(), hicann2.index()) self.assertEqual(str(wafer.status()), str(wafer2.status())) for row in Coordinate.iter_all(Coordinate.SynapseRowOnHICANN): d1 = hicann1.synapses[row].decoders d2 = hicann2.synapses[row].decoders self.assertEqual(d1, d2) w1 = hicann1.synapses[row].weights w2 = hicann2.synapses[row].weights self.assertEqual(w1, w2)
def test_hicann_merge(self): db = pysthal.YAMLHardwareDatabase() wafer = Wafer(20) db.add_wafer(wafer, SetupType.BSSWafer) for fpga in iter_all(FPGAOnWafer): db.add_fpga( FPGAGlobal(fpga, wafer), IPv4.from_string("192.168.20.{}".format(int(fpga) + 1))) for hicann in iter_all(HICANNOnWafer): db.add_hicann(HICANNGlobal(hicann, wafer), 4) yaml = str(db) # All HICANN entries should be merged into a single entry self.assertEqual(len(re.findall('hicann:', yaml)), 0) self.assertEqual(len(re.findall('hicanns:', yaml)), 1) self.assertEqual(len(re.findall('version: 4', yaml)), 1) self.assertEqual(len(re.findall('fpga:', yaml)), 48)
def test_manual_YAML3(self): """ Test hicann shortcut notation """ yaml = """ --- wafer: 1 setuptype: facetswafer fpgas: - fpga: 8 ip: "192.168.2.17" hicanns: version: 2 """ db = pysthal.YAMLHardwareDatabase() with tempfile.NamedTemporaryFile(mode="w+") as f: f.write(yaml) f.flush() db.load(f.name) self.assertEqual(SetupType.FACETSWafer, db.get_setup_type(Wafer(1))) for hicann in iter_all(HICANNOnWafer): hicann_global = HICANNGlobal(hicann, Wafer(1)) if hicann_global.toFPGAOnWafer() == FPGAOnWafer(8): self.assertTrue(db.has_hicann(hicann_global), "HICANN {} should be available".format(hicann)) else: self.assertFalse( db.has_hicann(hicann_global), "HICANN {} should not be available".format(hicann))
def f_fpga(coord): gcoord = C.FPGAGlobal(coord, WAFER) result = [] for dnc_f in C.iter_all(C.DNCOnFPGA): dnc = dnc_f.toDNCOnWafer(gcoord) result += hicanns_on_dnc(dnc) return result
def zero_all_iconv(self): """ Set I_conv to 0 for all neurons """ for nrn in C.iter_all(C.NeuronOnHICANN): self.set_value(nrn, neuron_parameter.I_convx, 0, False) self.set_value(nrn, neuron_parameter.I_convi, 0, False)
def _config_floating_gates(self, handle, hicann): all_rows = tuple(row for row in C.iter_all(C.FGRowOnFGBlock)) write_rows = [[row] * 4 for row in all_rows] rows = write_rows self.program_rows(handle, hicann, rows)
def setUp(self): """ Set up the unit test: A full reticle is allocated and complelty configured with zeroed floating gates. """ if None in (self.WAFER, self.DNC): raise unittest.SkipTest("No DNC selected, skipping hardware test") return self.data_adcs = {} # Dump data in case of an error in setup self.save_data() self.wafer = pysthal.Wafer(self.WAFER) self.reset_hicann_config() db = pysthal.MagicHardwareDatabase() self.wafer.connect(db) for hicann_c in self.hicanns: hicann = self.wafer[hicann_c] for analog in Coordinate.iter_all(Coordinate.AnalogOnHICANN): key = self.adc_key(hicann_c, analog) try: cfg = hicann.getADCConfig(analog) self.data_adcs[key] = (cfg.coord.value(), cfg.channel.value(), []) except RuntimeError: self.data_adcs[key] = (None, None, []) self.wafer.configure(pysthal.ParallelHICANNv4Configurator())
def program_rows_zero_neuron_values(self, handle, hicann, rows): fgc = hicann.floating_gates num_passes = fgc.getNoProgrammingPasses() for step in range(num_passes): fgconfig = fgc.getFGConfig(Enum(step)) logger = pylogging.get("test_fg_writing_precision") logger.debug("using FGConfig:") logger.debug(str(fgconfig)) for block in C.iter_all(C.FGBlockOnHICANN): pyhalbe.HICANN.set_fg_config(handle, block, fgconfig) for row_idx, row in enumerate(rows): writeDown = fgconfig.writeDown data = [ deepcopy(fgc[blk].getFGRow(row[int(blk.toEnum())])) for blk in C.iter_all(C.FGBlockOnHICANN) ] for i in range(len(data)): for nrn_c in C.iter_all(C.NeuronOnFGBlock): data[i].setNeuron(nrn_c, 0) res = pyhalbe.HICANN.set_fg_row_values(handle, row, data, writeDown) logger = pylogging.get("test_fg_writing_precision") logger.info("write result for step {} row {}".format( step, row_idx)) res_picklable = dict() for key in list(res.keys()): value = res[key] value_pick = [i.get_cell() for i in value] res_picklable[key] = value_pick logger.info(res_picklable) self._write_results_list.append( dict(step=step, row=row_idx, result=res_picklable, writeDown=writeDown, fgconfig=fgconfig))
def test_synapseswitch_exclusiveness(self): """ Check if checking of exclusiveness of synapse switch matrix works. Warning: Does not check for all possible valid and invalid combinations. """ from pyhalbe.HICANN import SynapseSwitch import pysthal from pyhalco_common import iter_all, SideHorizontal import pyhalco_hicann_v2 as C hicann = pysthal.HICANN() settings = pysthal.Settings.get() # check per vline for side in iter_all(SideHorizontal): for vline in iter_all(C.VLineOnHICANN): syn_drvs = [ syn_drv for syn_drv in vline.toSynapseDriverOnHICANN(side) ] for syn_drv1, syn_drv2 in zip(syn_drvs, syn_drvs[1:]): settings.synapse_switches.max_switches_per_column_per_side = 1 ssr1 = syn_drv1.toSynapseSwitchRowOnHICANN().line() ssr2 = syn_drv2.toSynapseSwitchRowOnHICANN().line() # one switch in vline -> ok hicann.synapse_switches.set(vline, ssr1, True) self.assertEqual(hicann.check(), "") # two switches in vline -> invalid hicann.synapse_switches.set(vline, ssr2, True) self.assertNotEqual(hicann.check(), "") settings.synapse_switches.max_switches_per_column_per_side = 2 self.assertEqual(hicann.check(), "") hicann.clear_l1_switches() # check per synapse switch row for syn_drv in C.iter_all(C.SynapseDriverOnHICANN): ssr = syn_drv.toSynapseSwitchRowOnHICANN() vlines = [vl for vl in SynapseSwitch.get_lines(ssr)] for vline1, vline2 in zip(vlines, vlines[1:]): settings.synapse_switches.max_switches_per_row = 1 # one switch in switch row -> ok hicann.synapse_switches.set(vline1, ssr.line(), True) self.assertEqual(hicann.check(), "") # two switches in switch row -> invalid hicann.synapse_switches.set(vline2, ssr.line(), True) self.assertNotEqual(hicann.check(), "") settings.synapse_switches.max_switches_per_row = 2 self.assertEqual(hicann.check(), "") hicann.clear_l1_switches()
def test_L1_detour_at_side_switch_usage(self): """ [155] 191 [223] 224 225 x226x {227} test detour and predecessor settings at the edge of a wafer """ pylogging.set_loglevel(pylogging.get("marocco"), pylogging.LogLevel.TRACE) pylogging.set_loglevel(pylogging.get("Calibtic"), pylogging.LogLevel.ERROR) self.marocco.persist = '' # or add test suite TestWithRuntime? runtime = Runtime(self.marocco.default_wafer) pynn.setup(marocco=self.marocco, marocco_runtime=runtime) settings = pysthal.Settings.get() settings.synapse_switches.max_switches_per_column_per_side = 1 settings.crossbar_switches.max_switches_per_row = 1 source = pynn.Population(1, pynn.IF_cond_exp, {}) target1 = pynn.Population(1, pynn.IF_cond_exp, {}) target2 = pynn.Population(1, pynn.IF_cond_exp, {}) proj = pynn.Projection( source, target1, pynn.AllToAllConnector(weights=1.)) proj = pynn.Projection( source, target2, pynn.AllToAllConnector(weights=1.)) source_hicann = C.HICANNOnWafer(Enum(227)) target1_hicann = C.HICANNOnWafer(Enum(155)) target2_hicann = C.HICANNOnWafer(Enum(225)) self.marocco.manual_placement.on_hicann(source, source_hicann) self.marocco.manual_placement.on_hicann(target1, target1_hicann) self.marocco.manual_placement.on_hicann(target2, target2_hicann) disabled_hicanns = [226, 263] wafer = self.marocco.default_wafer self.marocco.defects.set(pyredman.Wafer(runtime.wafer().index())) for hicann in C.iter_all(C.HICANNOnWafer): if hicann.toEnum().value() in disabled_hicanns: self.marocco.defects.wafer().hicanns().disable(C.HICANNGlobal(hicann, wafer)) continue pynn.run(0) pynn.end() for hicann in runtime.wafer().getAllocatedHicannCoordinates(): h = runtime.wafer()[hicann] print(hicann, h.check()) self.assertEqual(h.check(), "")
def hicann_out_test(self, hicann): """ Execute AnaRM test for a single HICANN: 1. Read two floating gate cells, expected value is 0 2. Update two floating gate rows with different values 3. Read updated rows """ data = {} hicann.analog.set_fg_left(Coordinate.AnalogOnHICANN(0)) hicann.analog.set_fg_right(Coordinate.AnalogOnHICANN(1)) fg_blocks = { Coordinate.AnalogOnHICANN(0): (Coordinate.FGBlockOnHICANN(Enum(0)), 300), Coordinate.AnalogOnHICANN(1): (Coordinate.FGBlockOnHICANN(Enum(3)), 600), } self.wafer.configure(UpdateFGRowConfigurator(self.ROW)) self.wafer.configure(SwitchAoutConfigurator(self.CELL)) for analog in Coordinate.iter_all(Coordinate.AnalogOnHICANN): data.update(self.read_trace(hicann, analog, 0)) for analog in Coordinate.iter_all(Coordinate.AnalogOnHICANN): block, dac = fg_blocks[analog] fgblock = hicann.floating_gates[block] for xvalue in Coordinate.iter_all( Coordinate.FGCellOnFGBlock.x_type): cell = Coordinate.FGCellOnFGBlock(xvalue, self.ROW) for cell in Coordinate.iter_all(Coordinate.FGCellOnFGBlock): fgblock.setRaw(cell, dac) self.wafer.configure(UpdateFGRowConfigurator(self.ROW)) self.wafer.configure(SwitchAoutConfigurator(self.CELL)) for analog in Coordinate.iter_all(Coordinate.AnalogOnHICANN): _, dac = fg_blocks[analog] data.update(self.read_trace(hicann, analog, dac)) return data
def test_external_sources_projections(self, params): nprojections = params[0] nsources = params[1] print((nprojections, nsources)) """ An external sources has multiple projections so it should be split if it wuld not be of size 1 so unfortunately the users would need to live with that. """ pylogging.set_loglevel(pylogging.get("marocco"), pylogging.LogLevel.TRACE) pylogging.set_loglevel(pylogging.get("Calibtic"), pylogging.LogLevel.ERROR) pynn.setup(marocco=self.marocco) self.marocco.neuron_placement.default_neuron_size(4) # ensure a limited synapse driver chain length. self.marocco.synapse_routing.driver_chain_length(3) # we expect synapse loss, but we dont care, as the source cant be split. # we want this tests not to throw exceptions. self.marocco.continue_despite_synapse_loss = True target = pynn.Population(1, pynn.IF_cond_exp, {}) hicann = C.HICANNOnWafer(Enum(100)) self.marocco.manual_placement.on_hicann(target, hicann) exsource = pynn.Population(nsources, pynn.SpikeSourcePoisson, {'rate': 1.}) for i in range(nprojections): proj = pynn.Projection(exsource, target, pynn.AllToAllConnector(weights=1.)) # access to proj so flake8 keeps silent proj.size pynn.run(0) pynn.end() results = self.load_results() synapses = results.synapse_routing.synapses() placement = results.placement for dnc in C.iter_all(C.DNCMergerOnWafer): PonDNC = placement.find(dnc) # PopulationOnDNC if PonDNC: ## if driver requirements exceeded, only one source should be ## placed on the DNC, but synapse loss is still expected if (nprojections > 4): # this number is just guessed self.assertTrue(len(PonDNC) <= 1) else: self.assertTrue(len(PonDNC) <= 12)
def config(self, fpga, handle, hicann): fg = hicann.floating_gates for fgpass in range(fg.getNoProgrammingPasses()): cfg = fg.getFGConfig(Enum(fgpass)) for block in Coordinate.iter_all(Coordinate.FGBlockOnHICANN): pyhalbe.HICANN.set_fg_config(handle, block, cfg) pyhalbe.HICANN.set_fg_row_values(handle, self.fg_row, fg, cfg.writeDown) # Update for VerifyConfiguration self.config_fg_stimulus(handle, hicann) self.flush_hicann(handle)
def test_ADCCalibration(self): """Tests ADCCalibration functionality.""" # generate fake calibration measurement vm = cal.VoltageMeasurement() for i in range(1, 9): dp = cal.DataPoint(0.2 + 0.01*i, i, 0.0001) vm.push_back(dp) # generate fake raw data to be converted to voltage data = pywrapstdvector.Vector_UInt16(np.array([1, 5, 3], dtype='uint16')) # create fresh calibration object adc = cal.ADCCalibration() # applying calibration on empty object should fail channel = pyhalco_hicann_v2.ChannelOnADC(0) self.assertRaises(RuntimeError, adc.apply, channel, data) # generate polynomials for each channel c_gnd = pyhalco_hicann_v2.ChannelOnADC(-1) for cc in pyhalco_hicann_v2.iter_all(pyhalco_hicann_v2.ChannelOnADC): if cc == c_gnd: # skip GND "channel" continue adc.makePolynomialTrafo(cc.value(), vm) # convert raw data to voltages res = adc.apply(channel, data) # check result self.assertAlmostEqual(res[0], 0.21, places=2) self.assertGreater(res[1], res[2]) with TemporaryDirectory() as tmp_dir: backend = loadXMLBackend(tmp_dir) md = cal.MetaData() id = pyhalbe.ADC.USBSerial("0") adc.store(backend, md, id) adc2 = cal.ADCCalibration() md2 = adc2.load(backend, id) del md2 res = adc2.apply(channel, data) self.assertAlmostEqual(res[0], 0.21, places=2) self.assertGreater(res[1], res[2]) data = np.array([1, 5, 3], dtype=np.ushort) res = adc.apply(channel, data) self.assertAlmostEqual(res[0], 0.21, places=2) self.assertGreater(res[1], res[2])
def test_crossbar_exclusiveness(self): """ Check if checking of exclusiveness of the crossbar switch matrix works. Warning: Does not check for all possible valid and invalid combinations. """ import pysthal import pyhalco_hicann_v2 as C hicann = pysthal.HICANN() settings = pysthal.Settings.get() # VLineOnHICANN::toHLineOnHICANN not implemented vline_to_hline = defaultdict(list) for hline in C.iter_all(C.HLineOnHICANN): for vline1, vline2 in zip(hline.toVLineOnHICANN(), hline.toVLineOnHICANN()[1:]): vline_to_hline[vline1].append(hline) settings.crossbar_switches.max_switches_per_row = 1 # one switch in hline hicann.crossbar_switches.set(vline1, hline, True) self.assertEqual(hicann.check(), "") # two switches in hline hicann.crossbar_switches.set(vline2, hline, True) self.assertNotEqual(hicann.check(), "") settings.crossbar_switches.max_switches_per_row = 2 self.assertEqual(hicann.check(), "") hicann.clear_l1_switches() for vline, hlines in vline_to_hline.items(): for hline1, hline2 in zip(hlines, hlines[1:]): settings.crossbar_switches.max_switches_per_column = 1 # one switch in vline hicann.crossbar_switches.set(vline, hline1, True) self.assertEqual(hicann.check(), "") # two switches in vline hicann.crossbar_switches.set(vline, hline2, True) self.assertNotEqual(hicann.check(), "") settings.crossbar_switches.max_switches_per_column = 2 self.assertEqual(hicann.check(), "") hicann.clear_l1_switches()
def test_external_sources_drivers(self, nsources): """ A lot external sources are placed no error should be thrown the sources should be split """ pylogging.set_loglevel(pylogging.get("marocco"), pylogging.LogLevel.DEBUG) pylogging.set_loglevel(pylogging.get("Calibtic"), pylogging.LogLevel.ERROR) pynn.setup(marocco=self.marocco) self.marocco.neuron_placement.default_neuron_size(4) # ensure a limited synapse driver chain length. self.marocco.synapse_routing.driver_chain_length(3) # if synapse loss occours we want to handle it on our own self.marocco.continue_despite_synapse_loss = True target = pynn.Population(1, pynn.IF_cond_exp, {}) hicann = C.HICANNOnWafer(Enum(100)) self.marocco.manual_placement.on_hicann(target, hicann) exsource = pynn.Population(nsources, pynn.SpikeSourcePoisson, {'rate': 1.}) proj = pynn.Projection(exsource, target, pynn.AllToAllConnector(weights=1.)) # access to proj so flake8 keeps silent proj.size pynn.run(0) pynn.end() results = self.load_results() synapses = results.synapse_routing.synapses() placement = results.placement # test for synapse loss self.assertEqual(nsources, synapses.size()) for dnc in C.iter_all(C.DNCMergerOnWafer): PonDNC = placement.find(dnc) # PopulationOnDNC if PonDNC: ## with a neuron size of 4 and a chain length of 3, ## around 12 sources can fit into a merger self.assertTrue(len(PonDNC) <= 12)
def test_dijkstra_routing(self): """ Integration test for Dijkstra-based L1 routing. Sets up a convoluted case that requires a convex route (which would not work using the backbone router). .------->------+ 167 168 169 170 | 206 v 240 241 242 | ^---<------+ """ pynn.setup(marocco=self.marocco) source = pynn.Population(1, pynn.IF_cond_exp, {}) target = pynn.Population(1, pynn.IF_cond_exp, {}) proj = pynn.Projection( source, target, pynn.AllToAllConnector(weights=0.004)) source_hicann = C.HICANNOnWafer(Enum(167)) target_hicann = C.HICANNOnWafer(Enum(240)) self.marocco.manual_placement.on_hicann(source, source_hicann) self.marocco.manual_placement.on_hicann(target, target_hicann) allowed_hicanns = [206] + list(range(167, 171)) + list(range(240, 243)) wafer = self.marocco.default_wafer self.marocco.defects.set(pyredman.Wafer()) for hicann in C.iter_all(C.HICANNOnWafer): if hicann.toEnum().value() in allowed_hicanns: continue self.marocco.defects.wafer().hicanns().disable(C.HICANNGlobal(hicann, wafer)) self.marocco.l1_routing.algorithm(self.marocco.l1_routing.dijkstra) pynn.run(0) pynn.end() results = self.load_results() synapses = results.synapse_routing.synapses() self.assertEqual(1, synapses.size())
def _config_floating_gates(self, handle, hicann): all_rows = tuple(row for row in C.iter_all(C.FGRowOnFGBlock)) int_op_rows = [[all_rows[1]] * 4] # left: 3 Iconvi, 17 Iconvx # right: 1 Iconvi 3 Iconvx iconv_rows = [ [all_rows[3], all_rows[1], all_rows[3], all_rows[1]], #pylint: disable=C0326 [all_rows[17], all_rows[3], all_rows[17], all_rows[3]] ] other_rows = [[row] * 4 for idx, row in enumerate(all_rows) if idx != 1 and idx != 3 and idx != 17] other_rows += [[all_rows[1], all_rows[17], all_rows[1], all_rows[17]]] self.program_rows(handle, hicann, int_op_rows) self.program_rows_zero_neuron_values(handle, hicann, iconv_rows) self.program_rows(handle, hicann, other_rows) self.program_rows(handle, hicann, iconv_rows)
def main(cls, *was_args, **was_kwargs): import argparse from pysthal.command_line_util import add_fpga_coordinate_options from pysthal.command_line_util import parse_hicann from pysthal.command_line_util import add_logger_options from pysthal.command_line_util import folder from pysthal.command_line_util import init_logger init_logger('INFO') parser = argparse.ArgumentParser(description='SthalHWTest: %s' % cls.__name__) add_fpga_coordinate_options(parser) parser.add_argument( '--hicann', action='store', required=False, type=parse_hicann, metavar='<enum>|<x>,<y>', dest='hicann', help="specify the HICANN on the wafer system to use") parser.add_argument('--hwdb', type=str, default=None, help="full path to hardware database") parser.add_argument('--data-output-dir', type=folder, default=None, help="Store outputs in this folder") parser.add_argument( '--replot', action='store_true', help='do not execute any test, just recreate the plot') add_logger_options(parser) args, argv = parser.parse_known_args() argv.insert(0, sys.argv[0]) if args.hwdb: settings = pysthal.Settings.get() settings.yaml_hardware_database_path = args.hwdb print("using non-default hardware database {}".format(args.hwdb)) if args.data_output_dir: output_dir = os.path.join( args.data_output_dir, 'wafer{}_dnc{:0>2}'.format(int(args.wafer), int(args.dnc.toEnum()))) if not os.path.exists(output_dir): os.makedirs(output_dir) else: output_dir = None cls.WAFER = args.wafer cls.DNC = args.dnc if args.hicann: cls.hicanns = [args.hicann] cls.DNC = Coordinate.DNCOnWafer((cls.hicanns[0].toDNCOnWafer())) else: cls.hicanns = [ hicann_on_dnc.toHICANNOnWafer(cls.DNC) for hicann_on_dnc in Coordinate.iter_all(Coordinate.HICANNOnDNC) ] cls.DATA_FOLDER = output_dir if args.replot: load_and_generate_plot(output_dir, args.wafer, args.dnc) return test_runner = None if output_dir: from xmlrunner import XMLTestRunner test_runner = XMLTestRunner(output=output_dir) cls.runner_outsuffix = test_runner.outsuffix unittest.main(argv=argv, testRunner=test_runner, *was_args, **was_kwargs)
def __init__(self): self.fg_block_values = dict() for blk in C.iter_all(C.FGBlockOnHICANN): self.fg_block_values[blk] = pyhalbe.HICANN.FGBlock(blk) self.modified_values = []
def test_FPGABEGTest(self): #configure DNC mergers mergers = HICANN.DNCMergerLine() for i in range(8): j = Coordinate.DNCMergerOnHICANN(i) if (i % 2): mergers[j].config = HICANN.Merger.RIGHT_ONLY else: mergers[j].config = HICANN.Merger.LEFT_ONLY mergers[j].slow = False mergers[j].loopback = not (i % 2) HICANN.set_dnc_merger(self.h, mergers) #configure DNC<->HICANN links gbit = DNC.GbitReticle() link = HICANN.GbitLink() for i in range(8): if (i % 2): link.dirs[i] = HICANN.GbitLink.Direction.TO_DNC else: link.dirs[i] = HICANN.GbitLink.Direction.TO_HICANN gbit[self.h.to_HICANNOnDNC()] = link HICANN.set_gbit_link(self.h, link) DNC.set_hicann_directions(self.fpga, self.dnc, gbit) #configure FPGA Background Generator bg = FPGA.BackgroundGenerator() bg.enable = True bg.poisson = False bg.seed = 12345 #cannot be zero bg.rate = 300 #in DNC-clock cycles bg.first_address = 2 bg.last_address = 3 #last address is greater or equal than first bg.hicann_number = self.h.coordinate().onDNC() bg.channels[0] = True #set active channels bg.channels[2] = True bg.channels[4] = True bg.channels[6] = True FPGA.set_fpga_background_generator(self.fpga, self.dnc, bg) HICANN.flush(self.h) #generate data container and receive data data = FPGA.PulseEventContainer() data.clear() data = FPGA.receive(self.fpga, self.dnc, 50000) #0,05 seconds print(str(data.size()) + " packets received") self.assertNotEqual(0, data.size()) number_count = 0 channel_count = 0 numbers = [] channels = [] for i in range(data.size()): numbers.append(int(data[i].getNeuronAddress())) channels.append(data[i].getChannel().value()) for j in range(64): if (numbers.count(j)): number_count += 1 for k in range(8): if (channels.count(k)): channel_count += 1 #check if number of different neuron numbers matches self.assertEqual(bg.last_address - bg.first_address + 1, number_count) #check if number of used channels matches self.assertEqual(bg.channels.count(), channel_count) #turn the BEG off bg.enable = False FPGA.set_fpga_background_generator(self.fpga, self.dnc, bg) #turn off the links to prevent packet collision for hicann in Coordinate.iter_all(Coordinate.HICANNOnDNC): link.dirs[hicann.toEnum().value()] = HICANN.GbitLink.Direction.OFF gbit[hicann] = link HICANN.set_gbit_link(self.h, link) DNC.set_hicann_directions(self.fpga, self.dnc, gbit) HICANN.flush(self.h)
fpga_c = hicann_c.toFPGAOnWafer() dnc_c = fpga_c.toDNCOnWafer() wafer = pysthal.Wafer(wafer_c) wafer.drop_defects() fpga = wafer[fpga_c] pll_frequency = args.pll * 1e6 fpga.commonFPGASettings().setPLL(pll_frequency) fpga.commonFPGASettings().setSynapseArrayReset(args.zero_syn) hicann = wafer[hicann_c] if args.zero_fg: set_floating_gate_to_zero(hicann) # blacklist all but the HICANN under test for h in C.iter_all(C.HICANNOnDNC): if h.toHICANNOnWafer(fpga_c) != hicann_c: fpga.setBlacklisted(h, True) if args.jtag: for h_hs in C.iter_all(C.HighspeedLinkOnDNC): if h_hs.toHICANNOnDNC().toHICANNOnWafer(dnc_c) == hicann_c: fpga.setHighspeed(h_hs.toHICANNOnDNC(), False) wafer.connect(pysthal.MagicHardwareDatabase()) if not args.zero_fg: wafer.configure(pysthal.JustResetHICANNConfigurator()) else: wafer.configure()
def config(self, fpga, handle, hicann): for fg_block in Coordinate.iter_all(Coordinate.FGBlockOnHICANN): pyhalbe.HICANN.set_fg_cell(handle, fg_block, self.fg_cell) self.config_analog_readout(handle, hicann) self.flush_hicann(handle)