def test_invalid_adds(self):
"""Check that errors a risen on invalid add calls"""
db = pysthal.YAMLHardwareDatabase()
with self.assertRaises(IndexError) as err:
db.add_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(4)),
IPv4.from_string("192.168.4.1"))
self.assertEqual("map::at", str(err.exception))
with self.assertRaises(IndexError) as err:
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4)), 2,
"X")
self.assertEqual("map::at", str(err.exception))
with self.assertRaises(IndexError) as err:
db.add_adc(FPGAGlobal(FPGAOnWafer(0), Wafer(4)), AnalogOnHICANN(0),
ADC("B201287"), ChannelOnADC(1), TriggerOnADC(0))
self.assertEqual("map::at", str(err.exception))
db.add_wafer(Wafer(4), SetupType.CubeSetup)
self.assertFalse(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(4))))
with self.assertRaises(IndexError) as err:
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4)), 2,
"X")
self.assertIn("map::at", str(err.exception))
def test_manual_YAML3(self):
"""
Test hicann shortcut notation
"""
yaml = """
---
wafer: 1
setuptype: facetswafer
fpgas:
- fpga: 8
ip: "192.168.2.17"
hicanns:
version: 2
"""
db = pysthal.YAMLHardwareDatabase()
with tempfile.NamedTemporaryFile(mode="w+") as f:
f.write(yaml)
f.flush()
db.load(f.name)
self.assertEqual(SetupType.FACETSWafer, db.get_setup_type(Wafer(1)))
for hicann in iter_all(HICANNOnWafer):
hicann_global = HICANNGlobal(hicann, Wafer(1))
if hicann_global.toFPGAOnWafer() == FPGAOnWafer(8):
self.assertTrue(db.has_hicann(hicann_global),
"HICANN {} should be available".format(hicann))
else:
self.assertFalse(
db.has_hicann(hicann_global),
"HICANN {} should not be available".format(hicann))
def get_all_functions(self, foo, fpga=False):
all = self.tree.xpath('/boost_serialization/type[text()="%s"]' % foo)
for n in all:
hicann, parameters = self.get_parameters(n)
if not fpga:
hc = HICANNGlobal(Enum(self.values_to_int(self.recursive_dict(hicann))['e']))
else:
hc = HICANNGlobal(Enum(self.values_to_int(self.recursive_dict(hicann))['wafer'])) #or 'value'
if self.coordinate.hicann() != hc and not fpga:
print("ignore non-matching hicanns...")
print("ignoring HICANN", hc, "(looking for", self.coordinate.hicann(), ")")
continue
else:
yield hicann, parameters
def test_adc_factory(self):
"""
Test that the ADC config is complete an has a factory set
"""
yaml = """
---
wafer: 20
setuptype: BSSWafer
macu: 0.0.0.0
macuversion: 1
fpgas:
- fpga: 0
ip: 192.168.1.1
adcs:
- fpga: 0
dnc_on_fpga: 0
analog: 0
adc: "03"
channel: 6
trigger: 1
- fpga: 0
dnc_on_fpga: 0
analog: 1
adc: "04"
remote_ip: "123.123.123.123"
remote_port: 321
channel: 6
trigger: 1
"""
db = pysthal.YAMLHardwareDatabase()
with tempfile.NamedTemporaryFile(mode="w+") as f:
f.write(yaml)
f.flush()
db.load(f.name)
hicann = HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(20))
analog = AnalogOnHICANN(0)
cfg = db.get_adc_of_hicann(hicann, analog)
self.assertEqual(cfg.channel, ChannelOnADC(6))
self.assertEqual(cfg.trigger, TriggerOnADC(1))
self.assertEqual(cfg.coord, ADC("03"))
self.assertEqual(cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
with self.assertRaises(TypeError):
# If cfg.factory would be a null pointer cfg.factory would be None
# and no error would be raised
f = cfg.factory
analog = AnalogOnHICANN(1)
cfg = db.get_adc_of_hicann(hicann, analog)
self.assertEqual(cfg.channel, ChannelOnADC(6))
self.assertEqual(cfg.trigger, TriggerOnADC(1))
self.assertEqual(cfg.coord, ADC("04"))
self.assertEqual(cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
with self.assertRaises(TypeError):
# If cfg.factory would be a null pointer cfg.factory would be None
# and no error would be raised
f = cfg.factory
def test_hicann_merge(self):
db = pysthal.YAMLHardwareDatabase()
wafer = Wafer(20)
db.add_wafer(wafer, SetupType.BSSWafer)
for fpga in iter_all(FPGAOnWafer):
db.add_fpga(
FPGAGlobal(fpga, wafer),
IPv4.from_string("192.168.20.{}".format(int(fpga) + 1)))
for hicann in iter_all(HICANNOnWafer):
db.add_hicann(HICANNGlobal(hicann, wafer), 4)
yaml = str(db)
# All HICANN entries should be merged into a single entry
self.assertEqual(len(re.findall('hicann:', yaml)), 0)
self.assertEqual(len(re.findall('hicanns:', yaml)), 1)
self.assertEqual(len(re.findall('version: 4', yaml)), 1)
self.assertEqual(len(re.findall('fpga:', yaml)), 48)
def test_serialization_versions(self):
hicann_with_backend_v0 = load.HicannWithBackend("share/redman/fake_blacklisting/v0/",
HICANNGlobal(), ignore_missing=False)
self.assertTrue(hicann_with_backend_v0.neurons().has_value())
wafer_with_backend_v0 = load.WaferWithBackend("share/redman/fake_blacklisting/v0/",
Wafer(), ignore_missing=False)
self.assertTrue(wafer_with_backend_v0.hicanns().has_value())
self.assertFalse(wafer_with_backend_v0.fpgas().has_value())
hicann_with_backend_v1 = load.HicannWithBackend("share/redman/fake_blacklisting/v1/",
HICANNGlobal(), ignore_missing=False)
self.assertFalse(hicann_with_backend_v1.neurons().has_value())
wafer_with_backend_v1 = load.WaferWithBackend("share/redman/fake_blacklisting/v1/",
Wafer(), ignore_missing=False)
self.assertFalse(wafer_with_backend_v1.hicanns().has_value())
self.assertFalse(wafer_with_backend_v1.fpgas().has_value())
wafer_with_backend_v2 = load.WaferWithBackend("share/redman/fake_blacklisting/v2/",
Wafer(), ignore_missing=False)
self.assertFalse(wafer_with_backend_v2.hicanns().has_value())
self.assertFalse(wafer_with_backend_v2.fpgas().has_value())
hicann_with_backend_v2 = load.HicannWithBackend("share/redman/fake_blacklisting/v2/",
HICANNGlobal(), ignore_missing=False)
self.assertFalse(hicann_with_backend_v2.neurons().has_value())
self.assertFalse(hicann_with_backend_v2.synapses().has_value())
self.assertFalse(hicann_with_backend_v2.drivers().has_value())
self.assertFalse(hicann_with_backend_v2.synaptic_inputs().has_value())
self.assertFalse(hicann_with_backend_v2.hbuses().has_value())
self.assertFalse(hicann_with_backend_v2.vbuses().has_value())
self.assertFalse(hicann_with_backend_v2.mergers0().has_value())
self.assertFalse(hicann_with_backend_v2.mergers1().has_value())
self.assertFalse(hicann_with_backend_v2.mergers2().has_value())
self.assertFalse(hicann_with_backend_v2.mergers3().has_value())
self.assertFalse(hicann_with_backend_v2.dncmergers().has_value())
self.assertFalse(hicann_with_backend_v2.synapserows().has_value())
self.assertFalse(hicann_with_backend_v2.analogs().has_value())
self.assertFalse(hicann_with_backend_v2.backgroundgenerators().has_value())
self.assertFalse(hicann_with_backend_v2.fgblocks().has_value())
self.assertFalse(hicann_with_backend_v2.vrepeaters().has_value())
self.assertFalse(hicann_with_backend_v2.hrepeaters().has_value())
self.assertFalse(hicann_with_backend_v2.synapseswitches().has_value())
self.assertFalse(hicann_with_backend_v2.crossbarswitches().has_value())
self.assertFalse(hicann_with_backend_v2.synapseswitchrows().has_value())
hicann_with_backend_v3 = load.HicannWithBackend("share/redman/fake_blacklisting/v3/",
HICANNGlobal(), ignore_missing=False)
self.assertFalse(hicann_with_backend_v3.neurons().has_value())
self.assertFalse(hicann_with_backend_v3.synapses().has_value())
self.assertFalse(hicann_with_backend_v3.drivers().has_value())
self.assertFalse(hicann_with_backend_v3.synaptic_inputs().has_value())
self.assertFalse(hicann_with_backend_v3.hbuses().has_value())
self.assertFalse(hicann_with_backend_v3.vbuses().has_value())
self.assertFalse(hicann_with_backend_v3.mergers0().has_value())
self.assertFalse(hicann_with_backend_v3.mergers1().has_value())
self.assertFalse(hicann_with_backend_v3.mergers2().has_value())
self.assertFalse(hicann_with_backend_v3.mergers3().has_value())
self.assertFalse(hicann_with_backend_v3.dncmergers().has_value())
self.assertFalse(hicann_with_backend_v3.synapserows().has_value())
self.assertFalse(hicann_with_backend_v3.analogs().has_value())
self.assertFalse(hicann_with_backend_v3.backgroundgenerators().has_value())
self.assertFalse(hicann_with_backend_v3.fgblocks().has_value())
self.assertFalse(hicann_with_backend_v3.vrepeaters().has_value())
self.assertFalse(hicann_with_backend_v3.hrepeaters().has_value())
self.assertFalse(hicann_with_backend_v3.synapseswitches().has_value())
self.assertFalse(hicann_with_backend_v3.crossbarswitches().has_value())
self.assertFalse(hicann_with_backend_v3.synapseswitchrows().has_value())
self.assertFalse(hicann_with_backend_v3.synapsearrays().has_value())
wafer_with_backend_v4 = load.WaferWithBackend("share/redman/fake_blacklisting/v4/",
Wafer(), ignore_missing=False)
self.assertFalse(wafer_with_backend_v4.hicanns().has_value())
self.assertFalse(wafer_with_backend_v4.fpgas().has_value())
def check(self, db):
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(4))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(4))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(5))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(5))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(6))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(6))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)),
Wafer(4))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(5))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)),
Wafer(5))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(6))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)),
Wafer(6))))
hicann = HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(4))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(0), Wafer(4)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201287"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201287"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
hicann = HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(3), Wafer(4)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201254"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201254"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
hicann = HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(5))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(0), Wafer(5)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201280"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201280"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
hicann = HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(5))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(3), Wafer(5)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201312"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201312"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
hicann = HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(6))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(0), Wafer(6)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201215"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201215"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
self.assertEqual(db.get_macu(Wafer(6)), IPv4())
self.assertEqual(db.get_macu(Wafer(7)),
IPv4.from_string("192.168.6.5"))
def test_interface(self):
"""
Test adding and removing entries
"""
db = pysthal.YAMLHardwareDatabase()
db.add_wafer(Wafer(4), SetupType.CubeSetup)
db.add_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(4)),
IPv4.from_string("192.168.4.1"))
db.add_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(4)),
IPv4.from_string("192.168.4.4"))
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4)), 2, "X")
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(89)), Wafer(4)), 4,
"v4-42")
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(116)), Wafer(4)), 2, "X")
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(4)), 4)
db.add_adc(FPGAGlobal(FPGAOnWafer(0), Wafer(4)), AnalogOnHICANN(0),
ADC("B201287"), ChannelOnADC(1), TriggerOnADC(0))
db.add_adc(FPGAGlobal(FPGAOnWafer(0), Wafer(4)), AnalogOnHICANN(1),
ADC("B201287"), ChannelOnADC(0), TriggerOnADC(0))
db.add_adc(FPGAGlobal(FPGAOnWafer(3), Wafer(4)), AnalogOnHICANN(0),
ADC("B201254"), ChannelOnADC(1), TriggerOnADC(0))
db.add_adc(FPGAGlobal(FPGAOnWafer(3), Wafer(4)), AnalogOnHICANN(1),
ADC("B201254"), ChannelOnADC(0), TriggerOnADC(0))
db.add_wafer(Wafer(5), SetupType.CubeSetup)
db.add_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(5)),
IPv4.from_string("192.168.5.1"))
db.add_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(5)),
IPv4.from_string("192.168.5.4"))
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(5)), 2)
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(5)), 4)
db.add_adc(FPGAGlobal(FPGAOnWafer(0), Wafer(5)), AnalogOnHICANN(0),
ADC("B201280"), ChannelOnADC(0), TriggerOnADC(0))
db.add_adc(FPGAGlobal(FPGAOnWafer(0), Wafer(5)), AnalogOnHICANN(1),
ADC("B201280"), ChannelOnADC(1), TriggerOnADC(0))
db.add_adc(FPGAGlobal(FPGAOnWafer(3), Wafer(5)), AnalogOnHICANN(0),
ADC("B201312"), ChannelOnADC(0), TriggerOnADC(0))
db.add_adc(FPGAGlobal(FPGAOnWafer(3), Wafer(5)), AnalogOnHICANN(1),
ADC("B201312"), ChannelOnADC(1), TriggerOnADC(0))
db.add_wafer(Wafer(6), SetupType.CubeSetup)
db.add_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(6)),
IPv4.from_string("192.168.6.1"))
db.add_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(6)),
IPv4.from_string("192.168.6.4"))
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(6)), 2, "X")
db.add_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(6)), 4)
db.add_adc(FPGAGlobal(FPGAOnWafer(0), Wafer(6)), AnalogOnHICANN(0),
ADC("B201215"), ChannelOnADC(0), TriggerOnADC(0))
db.add_adc(FPGAGlobal(FPGAOnWafer(0), Wafer(6)), AnalogOnHICANN(1),
ADC("B201215"), ChannelOnADC(1), TriggerOnADC(0))
db.add_wafer(Wafer(7), SetupType.BSSWafer,
IPv4.from_string("192.168.6.5"))
def check(self, db):
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(4))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(4))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(5))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(5))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(6))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(6))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)),
Wafer(4))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(5))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)),
Wafer(5))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(6))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)),
Wafer(6))))
hicann = HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(4))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(0), Wafer(4)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201287"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201287"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
hicann = HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(3), Wafer(4)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201254"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201254"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
hicann = HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(5))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(0), Wafer(5)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201280"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201280"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
hicann = HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(5))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(3), Wafer(5)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201312"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201312"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
hicann = HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(6))
self.assertEqual(hicann.toFPGAGlobal(),
FPGAGlobal(FPGAOnWafer(0), Wafer(6)))
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(0))
self.assertEqual(cfg.coord, ADC("B201215"))
self.assertEqual(cfg.channel, ChannelOnADC(0))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
cfg = db.get_adc_of_hicann(hicann, AnalogOnHICANN(1))
self.assertEqual(cfg.coord, ADC("B201215"))
self.assertEqual(cfg.channel, ChannelOnADC(1))
self.assertEqual(cfg.trigger, TriggerOnADC(0))
self.assertEqual(
cfg.loadCalibration,
pysthal.ADCConfig.CalibrationMode.LOAD_CALIBRATION)
self.assertEqual(db.get_macu(Wafer(6)), IPv4())
self.assertEqual(db.get_macu(Wafer(7)),
IPv4.from_string("192.168.6.5"))
check(self, db)
with tempfile.NamedTemporaryFile(mode="w+") as f:
db.store(f.name)
f.flush()
test_db = pysthal.YAMLHardwareDatabase(f.name)
check(self, test_db)
# Check that HICANN is removed, when fpga is removed
db.remove_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(4)))
self.assertFalse(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(4))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(4))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(5))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(5))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(0), Wafer(6))))
self.assertTrue(db.has_fpga(FPGAGlobal(FPGAOnWafer(3), Wafer(6))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4))))
self.assertFalse(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(4))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(5))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(5))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(6))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(6))))
#Check HICANN removal
db.remove_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4)))
self.assertFalse(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(4))))
self.assertFalse(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(4))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(5))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(5))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(88)), Wafer(6))))
self.assertTrue(
db.has_hicann(HICANNGlobal(HICANNOnWafer(Enum(144)), Wafer(6))))
'width': 4,
'values': self.out['syn_weights'+str(i)]['db']
}
merge(self.json_out, mydictupdates)
if __name__ == '__main__':
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('-i', '--input-file', help='Specify HALbe XML input file')
parser.add_argument('-o', '--output-file', help='Specify SimDenmem output file')
parser.add_argument('-N', '--neuron', default=0, type=int, help='Specify NeuronOnHICANN for simulation')
parser.add_argument('-H', '--hicann', default=216, type=int, help='Specify HICANNGlobal for simulation')
args = parser.parse_args()
inf = args.input_file
outf = args.output_file
nrn = args.neuron
# non-empty source file
assert os.path.exists(inf) and os.stat(inf).st_size != 0
# empty target file
#assert not os.path.exists(outf) or os.stat(outf).st_size == 0
ng = NeuronGlobal(NeuronOnHICANN(Enum(args.neuron)), HICANNGlobal(Enum(args.hicann)))
sim = HALbeXML2Sim2Denmem(inf, ng)
sim.extract()
sim.write(outf)