def setup_class(self): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # DECODER SIGNALS instr_hi = Signal(intbv(0)[8:]) pipe_dec_sig = decSignal() pipe_alu_op = Signal(alu_op_type.NOP) # Input Signals to Execute in_imm = Signal(intbv(0)[16:]) in_dm_addr = Signal(intbv(0)[DM_BITS:]) in_pc = Signal(intbv(0)[IM_BITS:]) out_acc = Signal(intbv(0)[16:]) out_dm_data = Signal(intbv(0)[16:]) fwd_accu = Signal(intbv(0)[16:]) ioin = inpSignal() self.signals = clock, reset, instr_hi, pipe_dec_sig, in_imm, \ in_dm_addr, in_pc, out_acc, out_dm_data self.decode_inst = decoder.pyleros_decoder(instr_hi, pipe_alu_op, pipe_dec_sig) self.exec_inst = execute.pyleros_exec(clock, reset, pipe_alu_op, pipe_dec_sig, in_imm, in_dm_addr, in_pc, \ out_acc, out_dm_data, fwd_accu, ioin, True) return self.decode_inst, self.exec_inst
def setup_class(self): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # DECODER SIGNALS instr_hi = Signal(intbv(0)[8:]) pipe_dec_sig = decSignal() pipe_alu_op = Signal(alu_op_type.NOP) # Input Signals to Execute in_imm = Signal(intbv(0)[16:]) in_dm_addr = Signal(intbv(0)[DM_BITS:]) in_pc = Signal(intbv(0)[IM_BITS:]) out_acc = Signal(intbv(0)[16:]) out_dm_data = Signal(intbv(0)[16:]) fwd_accu = Signal(intbv(0)[16:]) ioin = inpSignal() self.signals = clock, reset, instr_hi, pipe_dec_sig, in_imm, \ in_dm_addr, in_pc, out_acc, out_dm_data self.decode_inst = decoder.pyleros_decoder(instr_hi, pipe_alu_op, pipe_dec_sig) self.exec_inst = execute.pyleros_exec(clock, reset, pipe_alu_op, pipe_dec_sig, in_imm, in_dm_addr, in_pc, \ out_acc, out_dm_data, fwd_accu, ioin, True) return self.decode_inst, self.exec_inst
def setup_class(self): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # DECODER SIGNALS pipe_dec = decSignal() # Input Signals to Execute pipe_imme = Signal(intbv(0)[16:]) pipe_dm_addr = Signal(intbv(0)[DM_BITS:]) pipe_pc = Signal(intbv(0)[IM_BITS:]) back_acc = Signal(intbv(0)[16:]) back_dm_data = Signal(intbv(0)[16:]) self.signals = clock, reset, pipe_dec, pipe_imme, \ pipe_dm_addr, pipe_pc, back_acc, back_dm_data self.fwd_accu = Signal(intbv(0)[16:]) self.pipe_alu_op = Signal(alu_op_type.NOP) self.ioin = inpSignal()
def setup_class(self): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) ioin = inpSignal() ioout = outpSignal() self.signals = clock, reset, ioin, ioout
def conv_alu(): dec_sig = decSignal() alu_op = Signal(alu_op_type.NOP) acc = Signal(intbv(0)[16:]) pre_acc = Signal(intbv(0)[16:]) opd = Signal(intbv(0)[16:]) ioin = inpSignal() inst_alu = pyleros_alu(alu_op, dec_sig, acc, opd, pre_acc, ioin) inst_alu.convert(hdl = 'VHDL', path = PATH)
def conv_alu(): dec_sig = decSignal() alu_op = Signal(alu_op_type.NOP) acc = Signal(intbv(0)[16:]) pre_acc = Signal(intbv(0)[16:]) opd = Signal(intbv(0)[16:]) ioin = inpSignal() inst_alu = pyleros_alu(alu_op, dec_sig, acc, opd, pre_acc, ioin) inst_alu.convert(hdl='VHDL', path=PATH)
def conv_top_level(rom_file = 'sum_n.rom'): """ Conversion for the top level module pyleros.top """ clock = Signal(bool(0)) reset = ResetSignal(0, active =1 , async = True) ioin = inpSignal() ioout = outpSignal() inst_proc = pyleros(clock, reset, ioin, ioout, filename = ROM_PATH + rom_file) inst_proc.convert(hdl = 'VHDL', path = CONVERSION_PATH)
def conv_top_level(rom_file='sum_n.rom'): """ Conversion for the top level module pyleros.top """ clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) ioin = inpSignal() ioout = outpSignal() inst_proc = pyleros(clock, reset, ioin, ioout, filename=ROM_PATH + rom_file) inst_proc.convert(hdl='VHDL', path=CONVERSION_PATH)
def conv_exec(): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) pipe_dec = decSignal() # Input Signals to Execute pipe_imme = Signal(intbv(0)[16:]) pipe_dm_addr = Signal(intbv(0)[DM_BITS:]) pipe_pc = Signal(intbv(0)[IM_BITS:]) back_acc = Signal(intbv(0)[16:]) back_dm_data = Signal(intbv(0)[16:]) fwd_accu = Signal(intbv(0)[16:]) pipe_alu_op = Signal(alu_op_type.NOP) ioin = inpSignal() exec_inst = pyleros_exec(clock, reset, pipe_alu_op, pipe_dec, pipe_imme, pipe_dm_addr, pipe_pc, \ back_acc, back_dm_data, fwd_accu, ioin) exec_inst.convert(hdl='VHDL', path=PATH)
def conv_exec(): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) pipe_dec = decSignal() # Input Signals to Execute pipe_imme = Signal(intbv(0)[16:]) pipe_dm_addr = Signal(intbv(0)[DM_BITS:]) pipe_pc = Signal(intbv(0)[IM_BITS:]) back_acc = Signal(intbv(0)[16:]) back_dm_data = Signal(intbv(0)[16:]) fwd_accu = Signal(intbv(0)[16:]) pipe_alu_op = Signal(alu_op_type.NOP) ioin = inpSignal() exec_inst = pyleros_exec(clock, reset, pipe_alu_op, pipe_dec, pipe_imme, pipe_dm_addr, pipe_pc, \ back_acc, back_dm_data, fwd_accu, ioin) exec_inst.convert(hdl = 'VHDL', path = PATH)
def setup_class(self): clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # DECODER SIGNALS pipe_dec = decSignal() # Input Signals to Execute pipe_imme = Signal(intbv(0)[16:]) pipe_dm_addr = Signal(intbv(0)[DM_BITS:]) pipe_pc = Signal(intbv(0)[IM_BITS:]) back_acc = Signal(intbv(0)[16:]) back_dm_data = Signal(intbv(0)[16:]) self.signals = clock, reset, pipe_dec, pipe_imme, \ pipe_dm_addr, pipe_pc, back_acc, back_dm_data self.fwd_accu = Signal(intbv(0)[16:]) self.pipe_alu_op = Signal(alu_op_type.NOP) self.ioin = inpSignal()
def tb_fedec_top(): """Test the fetch/ decode module in pyleros """ def create_instr_list(): instr_list, bin_list = [], [] for instr in codes: if (not codes[instr][2]) or (instr == 'NOP') or (instr == 'LOADH') or (instr == 'STORE'): continue for trie in range(20): op1 = randrange(2**15) # 8-bit imm opd op2 = randrange(2**7) bin_code = codes[instr][0] # Immediate version bin_imme = bin_code | 0x01 instr_list.append([instr, op1, op2]) #Add operand op2 to instr bin_code = (bin_imme << 8) | (op2 & 0xff) bin_list.append(bin_code) return instr_list, bin_list clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # FEDEC SIGNALS back_acc, back_dm_data = [Signal(intbv(0)[16:])] * 2 pipe_imme = Signal(intbv(0)[16:]) pipe_dm_addr = Signal(intbv(0)[DM_BITS:]) pipe_pc = Signal(intbv(0)[IM_BITS:]) fwd_accu = Signal(intbv(0)[16:]) out_dec = decSignal() test_dec = decSignal() alu_op = Signal(alu_op_type.NOP) pipe_alu_op = Signal(alu_op_type.NOP) instr_hi = Signal(intbv(0)[8:]) dec_inst = decoder.pyleros_decoder(instr_hi, alu_op, test_dec) ioin = inpSignal() # ALU SIGNALS # out_list alu_acc = Signal(intbv(0)[16:]) alu_opd = Signal(intbv(0)[16:]) alu_res = Signal(intbv(0)[16:]) instr_list, bin_list = create_instr_list() alu_inst = alu.pyleros_alu(pipe_alu_op, out_dec, alu_acc, alu_opd, alu_res, ioin) fedec_inst = fedec.pyleros_fedec(clock, reset, back_acc, back_dm_data, fwd_accu, pipe_alu_op, out_dec, pipe_imme, pipe_dm_addr, pipe_pc, filename=bin_list, debug = True) @always(delay(100)) def tbclk(): clock.next = not clock @instance def tbstim(): # To start the fetch/decoding # reset.next = not reset.active print("bin_list") for i in range(10): print(bin_list[i], instr_list[i][2]) # In the first cycle nothing happens since # only the instuction is updated, and the # decoder, the output from fedec doesn't change # till after the second cycle. yield clock.posedge ninstr = len(instr_list) for addr in range(1,ninstr - 1): # if addr == 10: # raise StopSimulation print(addr) # for the alu, op1 signifies the acc adn # op2 the opd instr, op1, op2 = instr_list[addr] instr_hi.next = (codes[instr][0] | 0x01) yield clock.posedge yield delay(3) for sig in dlist: assert test_dec.signals[int(sig)] == out_dec.signals[int(sig)] print("Cmp Imm", op2, pipe_imme) alu_acc.next = op1 alu_opd.next = pipe_imme yield delay(3) # print("alu ops", op1, alu_acc, pipe_imme, alu_opd) # print("alu types", type(op1), type(alu_acc), type(pipe_imme), type(alu_opd)) # print(out_dec[int(dec_op_type.add_sub)], out_dec[int(dec_op_type.log_add)]) #check for correct result if instr == 'NOP': pass elif instr == 'ADD': assert alu_res == int(op1) + int(op2) elif instr == 'SUB': assert alu_res == ((op1 - op2) & 0xffff) elif instr == 'SHR': assert alu_res == (op1 & 0xffff) >> 1 elif instr == 'AND': assert alu_res == (op1 & op2) & 0xffff elif instr == 'OR': assert alu_res == (op1 | op2) & 0xffff elif instr == 'XOR': assert alu_res == (op1 ^ op2) & 0xffff elif instr == 'LOAD': assert alu_res == op2 & 0xffff raise StopSimulation return instances()
def tb_alu_top(imen=False): """Test the alu module in pyleros """ clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # DECODER SIGNALS instr_hi = Signal(intbv(0)[8:]) dec_signal = decSignal() alu_op = Signal(alu_op_type.NOP) ioin = inpSignal() decode_inst = decoder.pyleros_decoder(instr_hi, alu_op, dec_signal) # ALU SIGNALS # dec_signal alu_acc = Signal(intbv(0)[16:]) alu_opd = Signal(intbv(0)[16:]) alu_res = Signal(intbv(0)[16:]) alu_inst = alu.pyleros_alu(alu_op, dec_signal, alu_acc, alu_opd, alu_res, ioin) rd_addr = Signal(intbv(0)[IM_BITS:]) rd_data = Signal(intbv(0)[16:]) instr_list, bin_list = [], [] # Create instruction memory if enabled. if imen: for instr in codes: for trie in range(20): op1 = randrange(2**15) op2 = randrange(2**15) bin_code = codes[instr][0] instr_list.append([instr, op1, op2]) bin_code = (bin_code << 8) bin_list.append(bin_code) inst_im = rom.pyleros_im(rd_addr, rd_data, IM_array=tuple(bin_list)) @always(delay(10)) def tbclk(): clock.next = not clock # def _bench_alu(): @instance def tbstim(): for i in range(5): yield clock.posedge if imen: ninstr = len(instr_list) for addr in range(ninstr): instr, op1, op2 = instr_list[addr] rd_addr.next = intbv(addr)[IM_BITS:] yield clock.posedge yield delay(2) assert rd_data == bin_list[rd_addr] upp = (int(rd_data)) >> 8 assert upp == codes[instr][0] instr_hi.next = intbv(upp)[8:] alu_acc.next = op1 alu_opd.next = op2 yield delay(33) #check for correct result if instr == 'NOP': pass elif instr == 'ADD': assert alu_res == ((op1 + op2) & 0xffff) elif instr == 'SUB': assert alu_res == ((op1 - op2) & 0xffff) elif instr == 'SHR': assert alu_res == (op1 & 0xffff) >> 1 elif instr == 'AND': assert alu_res == (op1 & op2) & 0xffff elif instr == 'OR': assert alu_res == (op1 | op2) & 0xffff elif instr == 'XOR': assert alu_res == (op1 ^ op2) & 0xffff elif instr == 'LOAD': assert alu_res == op2 & 0xffff else: for instr in codes: for i in range(10): # Choose random operands op1 = randrange(2**15) op2 = randrange(2**15) # Set the decoder input instr_op = codes[instr][0] instr_hi.next = instr_op alu_acc.next = op1 alu_opd.next = op2 # Wait for operation yield delay(33) #check for correct result if instr == 'NOP': pass elif instr == 'ADD': assert alu_res == ((op1 + op2) & 0xffff) elif instr == 'SUB': assert alu_res == ((op1 - op2) & 0xffff) elif instr == 'SHR': assert alu_res == (op1 & 0xffff) >> 1 elif instr == 'AND': assert alu_res == (op1 & op2) & 0xffff elif instr == 'OR': assert alu_res == (op1 | op2) & 0xffff elif instr == 'XOR': assert alu_res == (op1 ^ op2) & 0xffff elif instr == 'LOAD': assert alu_res == op2 & 0xffff raise StopSimulation return instances() #, decode_inst
def tb_alu_top(imen=False): """Test the alu module in pyleros """ clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # DECODER SIGNALS instr_hi = Signal(intbv(0)[8:]) dec_signal = decSignal() alu_op = Signal(alu_op_type.NOP) ioin = inpSignal() decode_inst = decoder.pyleros_decoder(instr_hi, alu_op, dec_signal) # ALU SIGNALS # dec_signal alu_acc = Signal(intbv(0)[16:]) alu_opd = Signal(intbv(0)[16:]) alu_res = Signal(intbv(0)[16:]) alu_inst = alu.pyleros_alu(alu_op, dec_signal, alu_acc, alu_opd, alu_res, ioin) rd_addr = Signal(intbv(0)[IM_BITS:]) rd_data = Signal(intbv(0)[16:]) instr_list, bin_list = [], [] # Create instruction memory if enabled. if imen: for instr in codes: for trie in range(20): op1 = randrange(2**15) op2 = randrange(2**15) bin_code = codes[instr][0] instr_list.append([instr, op1, op2]) bin_code = (bin_code << 8) bin_list.append(bin_code) inst_im = rom.pyleros_im(rd_addr, rd_data, IM_array=tuple(bin_list)) @always(delay(10)) def tbclk(): clock.next = not clock # def _bench_alu(): @instance def tbstim(): for i in range(5): yield clock.posedge if imen: ninstr = len(instr_list) for addr in range(ninstr): instr, op1, op2 = instr_list[addr] rd_addr.next = intbv(addr)[IM_BITS:] yield clock.posedge yield delay(2) assert rd_data == bin_list[rd_addr] upp = (int(rd_data)) >> 8 assert upp == codes[instr][0] instr_hi.next = intbv(upp)[8:] alu_acc.next = op1 alu_opd.next = op2 yield delay(33) #check for correct result if instr == 'NOP': pass elif instr == 'ADD': assert alu_res == ((op1 + op2) & 0xffff) elif instr == 'SUB': assert alu_res == ((op1 - op2) & 0xffff) elif instr == 'SHR': assert alu_res == (op1 & 0xffff) >> 1 elif instr == 'AND': assert alu_res == (op1 & op2) & 0xffff elif instr == 'OR': assert alu_res == (op1 | op2) & 0xffff elif instr == 'XOR': assert alu_res == (op1 ^ op2) & 0xffff elif instr == 'LOAD': assert alu_res == op2 & 0xffff else: for instr in codes: for i in range(10): # Choose random operands op1 = randrange(2**15) op2 = randrange(2**15) # Set the decoder input instr_op = codes[instr][0] instr_hi.next = instr_op alu_acc.next = op1 alu_opd.next = op2 # Wait for operation yield delay(33) #check for correct result if instr == 'NOP': pass elif instr == 'ADD': assert alu_res == ((op1 + op2) & 0xffff) elif instr == 'SUB': assert alu_res == ((op1 - op2) & 0xffff) elif instr == 'SHR': assert alu_res == (op1 & 0xffff) >> 1 elif instr == 'AND': assert alu_res == (op1 & op2) & 0xffff elif instr == 'OR': assert alu_res == (op1 | op2) & 0xffff elif instr == 'XOR': assert alu_res == (op1 ^ op2) & 0xffff elif instr == 'LOAD': assert alu_res == op2 & 0xffff raise StopSimulation return instances() #, decode_inst
def tb_fedec_top(): """Test the fetch/ decode module in pyleros """ def create_instr_list(): instr_list, bin_list = [], [] for instr in codes: if (not codes[instr][2]) or (instr == 'NOP') or ( instr == 'LOADH') or (instr == 'STORE'): continue for trie in range(20): op1 = randrange(2**15) # 8-bit imm opd op2 = randrange(2**7) bin_code = codes[instr][0] # Immediate version bin_imme = bin_code | 0x01 instr_list.append([instr, op1, op2]) #Add operand op2 to instr bin_code = (bin_imme << 8) | (op2 & 0xff) bin_list.append(bin_code) return instr_list, bin_list clock = Signal(bool(0)) reset = ResetSignal(0, active=1, async=True) # FEDEC SIGNALS back_acc, back_dm_data = [Signal(intbv(0)[16:])] * 2 pipe_imme = Signal(intbv(0)[16:]) pipe_dm_addr = Signal(intbv(0)[DM_BITS:]) pipe_pc = Signal(intbv(0)[IM_BITS:]) fwd_accu = Signal(intbv(0)[16:]) out_dec = decSignal() test_dec = decSignal() alu_op = Signal(alu_op_type.NOP) pipe_alu_op = Signal(alu_op_type.NOP) instr_hi = Signal(intbv(0)[8:]) dec_inst = decoder.pyleros_decoder(instr_hi, alu_op, test_dec) ioin = inpSignal() # ALU SIGNALS # out_list alu_acc = Signal(intbv(0)[16:]) alu_opd = Signal(intbv(0)[16:]) alu_res = Signal(intbv(0)[16:]) instr_list, bin_list = create_instr_list() alu_inst = alu.pyleros_alu(pipe_alu_op, out_dec, alu_acc, alu_opd, alu_res, ioin) fedec_inst = fedec.pyleros_fedec(clock, reset, back_acc, back_dm_data, fwd_accu, pipe_alu_op, out_dec, pipe_imme, pipe_dm_addr, pipe_pc, filename=bin_list, debug=True) @always(delay(100)) def tbclk(): clock.next = not clock @instance def tbstim(): # To start the fetch/decoding # reset.next = not reset.active print("bin_list") for i in range(10): print(bin_list[i], instr_list[i][2]) # In the first cycle nothing happens since # only the instuction is updated, and the # decoder, the output from fedec doesn't change # till after the second cycle. yield clock.posedge ninstr = len(instr_list) for addr in range(1, ninstr - 1): # if addr == 10: # raise StopSimulation print(addr) # for the alu, op1 signifies the acc adn # op2 the opd instr, op1, op2 = instr_list[addr] instr_hi.next = (codes[instr][0] | 0x01) yield clock.posedge yield delay(3) for sig in dlist: assert test_dec.signals[int(sig)] == out_dec.signals[int( sig)] print("Cmp Imm", op2, pipe_imme) alu_acc.next = op1 alu_opd.next = pipe_imme yield delay(3) # print("alu ops", op1, alu_acc, pipe_imme, alu_opd) # print("alu types", type(op1), type(alu_acc), type(pipe_imme), type(alu_opd)) # print(out_dec[int(dec_op_type.add_sub)], out_dec[int(dec_op_type.log_add)]) #check for correct result if instr == 'NOP': pass elif instr == 'ADD': assert alu_res == int(op1) + int(op2) elif instr == 'SUB': assert alu_res == ((op1 - op2) & 0xffff) elif instr == 'SHR': assert alu_res == (op1 & 0xffff) >> 1 elif instr == 'AND': assert alu_res == (op1 & op2) & 0xffff elif instr == 'OR': assert alu_res == (op1 | op2) & 0xffff elif instr == 'XOR': assert alu_res == (op1 ^ op2) & 0xffff elif instr == 'LOAD': assert alu_res == op2 & 0xffff raise StopSimulation return instances()