def construct(s): s.in_ = InPort(Bits32) s.out = OutPort(Bits32) s.v = VReg() s.v.in_ //= s.in_ s.v.out //= s.out s.verilog_translate_import = True
def construct(s): s.in_ = InPort(Bits32) s.out = OutPort(Bits32) @s.update_on_edge def upblk(): s.out = s.in_
def construct(s): s.in_ = [InPort(Bits1) for _ in range(4)] s.out = OutPort(Bits1) @s.update def upblk(): s.out = s.in_[4]
def construct(s): s.in_ = InPort(Bits32) s.out = OutPort(Bits64) @s.update def upblk(): s.out = concat(s.in_, Bits32(0))
def construct(s): s.in_ = [InPort(Bits32) for _ in range(2)] s.out = OutPort(Bits64) @s.update def upblk(): s.out = concat(s.in_[0], s.in_[1])
def construct( s ): s.in_ = InPort( Bits16 ) s.out = OutPort( Bits16 ) @s.update def multi_components_B(): s.out = s.in_
def construct(s): s.in_ = InPort(Bits32) s.out = OutPort(Bits32) @s.update_ff def upblk(): s.out <<= s.in_
def construct( s ): s.in_ = InPort( Bits32 ) s.inner = Inner() s.out = OutPort( Bits32 ) connect( s.in_, s.inner.in_) connect( s.inner.out, s.out )
def construct(s): s.in_ = InPort(Bits8) s.out = OutPort(Bits16) @s.update def upblk(): s.out = concat(s, s.in_)
def construct(s): s.in_ = InPort(Bits32) s.out = OutPort(Bits32) s.set_metadata(VerilogPlaceholderPass.port_map, { s.in_: "d", s.out: "q", })
def construct(s, shamt=1): s.in_ = InPort(Bits32) s.out = OutPort(Bits32) @s.update def up_real(): s.out = s.in_ + shamt
def construct(s, nports, nbits): s.in_ = [InPort(mk_bits(nbits)) for _ in range(nports)] s.out = [OutPort(mk_bits(nbits)) for _ in range(nports)] s.set_metadata(VerilogPlaceholderPass.params, { 'num_ports': nports, 'bitwidth': nbits, })
def construct(s, nbits=1): s.in_ = InPort(nbits) s.out = OutPort(nbits) @update def up_x2(): s.out @= s.in_ << 1
def construct(s): s.in_ = InPort(Bits16) s.out = OutPort(Bits32) s.inner = FooStruct(16) s.inner.in_ //= s.in_ connect(s.inner.out.b, s.out)
def construct( s ): s.in_ = InPort( Bits16 ) s.out = OutPort( Bits8 ) @s.update def mismatch_width_assign(): s.out = s.in_
def construct(s): s.buf = InPort(Bits32) s.out = OutPort(Bits32) @s.update def upblk(): s.out = s.buf
def construct( s ): s.in_ = InPort( Bits16 ) s.out = OutPort( Bits16 ) @s.update def bits_basic(): s.out = s.in_ + Bits16( 10 )
def construct( s ): s.in_ = InPort( B ) s.out = OutPort( Bits32 ) @s.update def upblk(): u = s.in_ s.out = u.foo
def construct( s ): s.in_ = InPort( Bits16 ) s.out = [ OutPort( Bits8 ) for _ in range(2) ] @s.update def upblk(): for i in range(2): s.out[i] = s.in_[i*8 : i*8 + 8]
def construct( s ): s.in_ = InPort( Bits4 ) s.out = [ OutPort( Bits1 ) for _ in range(5) ] s.comp_array = [ B() for _ in range(5) ] @s.update def upblk(): s.out = s.comp_array[ 0 ].out
def construct(s): s.in_ = InPort(B) s.out = OutPort(Bits96) @s.update def upblk(): s.out = concat(s.in_.bar[0], s.in_.c.woof, s.in_.foo)
def construct( s ): s.in_ = InPort( Bits32 ) s.idx = B() s.out = OutPort( Bits4 ) @s.update def upblk(): s.out = s.in_[ 0:s.idx ]
def construct(s): s.in_ = InPort(Bits32) s.out = OutPort(Bits64) @s.update def upblk(): s.out = zext(s.in_, 64)
def construct(s): s.in_ = InPort(B) s.out = OutPort(Bits1) @s.update def upblk(): s.out = Bits1(1) + s.in_
def construct(s): s.in_ = InPort(Bits64) s.out = OutPort(Bits32) @s.update def upblk(): s.out = s.in_[4:36]
def construct(s, nbits=0): s.in_ = InPort(mk_bits(nbits)) s.out = OutPort(mk_bits(nbits)) s.w = Wire(mk_bits(nbits)) connect(s.w, s.out) s.inner = Foo(32)(in_=s.in_, out=s.w)
def construct(s): s.in_ = InPort(Bits8) s.out = OutPort(Bits16) @s.update def upblk(): s.out = sext(s.in_, 4)
def construct(s, nbits=0): s.in_ = InPort(mk_bits(nbits)) s.out = OutPort(mk_bits(nbits)) @s.update def up_x2(): s.out = s.in_ << 1
def construct(s): s.in_ = InPort(Bits4) s.out = OutPort(Bits1) @s.update def upblk(): s.out = s.in_[4]
def construct( s ): foo = InPort( B ) s._foo = foo s.out = OutPort( Bits32 ) @s.update def upblk(): s.out = foo.foo