def _gen_verilog_wrapper(s, m, cfg, irepr):
# By default use single underscore as separator
rtlir_ports = gen_mapped_ports(m, cfg.port_map, cfg.has_clk,
cfg.has_reset, '_')
all_port_names = list(map(lambda x: x[1], rtlir_ports))
if not cfg.params:
parameters = irepr.get_params()
else:
parameters = cfg.params.items()
# Port definitions of wrapper
ports = []
for idx, (_, name, p, _) in enumerate(rtlir_ports):
if name:
if isinstance(p, rt.Array):
n_dim = p.get_dim_sizes()
s_dim = ''.join([f'[0:{idx-1}]' for idx in n_dim])
p = p.get_next_dim_type()
else:
s_dim = ''
ports.append(
f" {p.get_direction()} logic [{p.get_dtype().get_length()}-1:0]"\
f" {name} {s_dim}{'' if idx == len(rtlir_ports)-1 else ','}"
)
# The wrapper has to have an unused clk port to make verilator
# VCD tracing work.
if 'clk' not in all_port_names:
ports.insert(0, ' input logic clk,')
if 'reset' not in all_port_names:
ports.insert(0, ' input logic reset,')
# Parameters passed to the module to be parametrized
params = [
f" .{param}( {val} ){'' if idx == len(parameters)-1 else ','}"\
for idx, (param, val) in enumerate(parameters)
]
# Connections between top module and inner module
connect_ports = [
f" .{name}( {name} ){'' if idx == len(rtlir_ports)-1 else ','}"\
for idx, (_, name, p, _) in enumerate(rtlir_ports) if name
]
lines = [
f"module {cfg.pickled_top_module}",
"(",
] + ports + [
");",
f" {cfg.top_module}",
" #(",
] + params + [
" ) v",
" (",
] + connect_ports + [
" );",
"endmodule",
]
template_lines = [
"module {top_module_name}",
"(",
] + ports + [
");",
f" {cfg.top_module}",
" #(",
] + params + [
" ) v",
" (",
] + connect_ports + [
" );",
"endmodule",
]
return '\n'.join(line for line in lines), '\n'.join(
line for line in template_lines)
def local_do_test(m):
m.elaborate()
result = gen_mapped_ports(m, {})
assert result == m._ref_ports