def _subcomp_port_gen( c_name, c_id, n_dim, port_decls ):
p_wire_tplt = "logic {packed_type: <8} {id_};"
p_conn_tplt = ".{port_id: <15}( {port_wire_id} )"
template = \
"""\
{port_wires}
{c_name} {c_id}
(
{port_conn_decls}
);\
"""
if not n_dim:
p_wires, p_conns = [], []
for port in port_decls:
msb, _id = port["msb"], port["id_"]
id_ = c_id + "__" + _id
port_id = _id
port_wire_id = ( f"{c_id}__{_id}" ).center( 25 )
packed_type = f"[{msb}:0]"
p_wires.append( p_wire_tplt.format( **locals() ) )
p_conns.append( p_conn_tplt.format( **locals() ) )
make_indent( p_wires, 1 )
make_indent( p_conns, 2 )
port_wires = "\n".join( p_wires )
port_conn_decls = ",\n".join( p_conns )
return [ template.format( **locals() ) ]
else:
ret = []
for i in range( n_dim[0] ):
ret += _subcomp_port_gen( c_name, c_id+"__"+str(i), n_dim[1:], port_decls )
return ret
def rtlir_tr_subcomp_decls( s, subcomp_decls ):
port_decls, wire_decls, conns = [], [], []
for subcomp_decl in subcomp_decls:
port_decls.extend( subcomp_decl["port_decls"] )
wire_decls.extend( subcomp_decl["wire_decls"] )
conns.extend( subcomp_decl["connections"] )
make_indent( wire_decls, 1 )
make_indent( conns, 1 )
return {
"port_decls" : "\n\n".join( port_decls ),
"wire_decls" : "\n".join( wire_decls ),
"connections" : "\n".join( conns )
}
def visit_For(s, node):
node.start._top_expr = 1
node.end._top_expr = 1
node.step._top_expr = 1
# Yosys-comptabile Verilog for loop
src = []
body = []
loop_var = s.visit(node.var)
start = s.visit(node.start)
end = s.visit(node.end)
loop_var = "__loopvar__" + s.blk.__name__ + "_" + loop_var
if loop_var not in s.loopvars:
s.loopvars.add(loop_var)
begin = ' begin' if len(node.body) > 1 else ''
cmp_op = '<' if node.step.value > 0 else '<'
inc_op = '+' if node.step.value > 0 else '-'
step_abs = s.visit(node.step)
step_abs = step_abs if node.step.value > 0 else step_abs[1:]
for stmt in node.body:
body.extend(s.visit(stmt))
make_indent(body, 1)
for_begin = \
'for ( {v} = {s}; {v} {comp} {t}; {v} = {v} {inc} {stp} ){begin}'.format(
v = loop_var, s = start, t = end, stp = step_abs,
comp = cmp_op, inc = inc_op, begin = begin
)
# Assemble for statement
src.extend([for_begin])
src.extend(body)
if len(node.body) > 1:
src.extend(['end'])
return src
def rtlir_tr_port_decls(s, port_decls):
ret = {"port_decls": [], "wire_decls": [], "connections": []}
for port_decl in port_decls:
ret["port_decls"] += port_decl["port_decls"]
ret["wire_decls"] += port_decl["wire_decls"]
ret["connections"] += port_decl["connections"]
make_indent(ret["port_decls"], 1)
make_indent(ret["wire_decls"], 1)
make_indent(ret["connections"], 1)
ret["port_decls"] = ",\n".join(ret["port_decls"])
ret["wire_decls"] = "\n".join(ret["wire_decls"])
ret["connections"] = "\n".join(ret["connections"])
return ret
def rtlir_tr_interface_decls(s, ifc_decls):
port_decls, wire_decls, connections = [], [], []
for ifc_decl in ifc_decls:
port_decls += ifc_decl["port_decls"]
wire_decls += ifc_decl["wire_decls"]
connections += ifc_decl["connections"]
make_indent(port_decls, 1)
make_indent(wire_decls, 1)
make_indent(connections, 1)
return {
"port_decls": ",\n".join(port_decls),
"wire_decls": "\n".join(wire_decls),
"connections": "\n".join(connections),
}
def rtlir_tr_wire_decls(s, wire_decls):
wires = []
for wire_decl in wire_decls:
wires += wire_decl
make_indent(wires, 1)
return '\n'.join(wires)
def rtlir_tr_behavioral_tmpvars(s, tmpvars):
_tmpvars = []
for tmpvar in tmpvars:
_tmpvars += tmpvar
make_indent(_tmpvars, 1)
return '\n'.join(_tmpvars)