def run_sim(s, th):
vcd_file_name = s.__class__.cmdline_opts["dump_vcd"]
max_cycles = s.__class__.cmdline_opts["max_cycles"] or 10000
# Translate the DUT and import it back in using the yosys backend.
th.elaborate()
# Check command line arguments for vcd dumping
if vcd_file_name:
th.set_metadata(VcdGenerationPass.vcd_file_name, vcd_file_name)
th.dut.set_metadata(YosysVerilatorImportPass.vl_trace, True)
th.dut.set_metadata(YosysVerilatorImportPass.vl_trace_filename,
vcd_file_name)
# Translate the DUT and import it back in using the yosys backend.
th.dut.set_metadata(YosysTranslationImportPass.enable, True)
th = YosysTranslationImportPass()(th)
# Create a simulator
th.apply(DefaultPassGroup())
# Tick the simulator
while not th.done() and th.sim_cycle_count() < max_cycles:
th.sim_tick()
# Check timeout
assert th.sim_cycle_count() < max_cycles
finalize_verilator(th)
def checksum_vrtl( words ):
# Convert input words into bits
bits_in = words_to_b128( words )
# Instantiate and elaborate the checksum unit
dut = ChecksumRTL()
dut.elaborate()
# Translate the checksum unit and import it back in using the yosys
# backend
dut.set_metadata( YosysTranslationImportPass.enable, True )
dut = YosysTranslationImportPass()( dut )
# Create a simulator
dut.elaborate()
dut.apply( DefaultPassGroup() )
dut.sim_reset()
# Wait until the checksum unit is ready to receive input
dut.send.rdy @= 1
while not dut.recv.rdy:
dut.sim_tick()
# Feed in the input
dut.recv.en @= 1
dut.recv.msg @= bits_in
dut.sim_tick()
# Wait until the checksum unit is about to send the message
while not dut.send.en:
dut.sim_tick()
# Return the result
return dut.send.msg
def local_do_test( _m ):
_m.elaborate()
if not hasattr( _m, "_no_trans_import" ):
_m.set_metadata( YosysTranslationImportPass.enable, True )
_m.apply( VerilogPlaceholderPass() )
m = YosysTranslationImportPass()( _m )
sim = TestVectorSimulator( m, _m._tvs, _m._tv_in, _m._tv_out )
sim.run_test()
def run_sim(s, th, max_cycles=1000):
# Translate the DUT and import it back in using the yosys backend.
th.elaborate()
th.dut.set_metadata(YosysTranslationImportPass.enable, True)
th = YosysTranslationImportPass()(th)
# Create a simulator
th.apply(DefaultPassGroup())
# Tick the simulator
while not th.done() and th.sim_cycle_count() < max_cycles:
th.sim_tick()
# Check timeout
assert th.sim_cycle_count() < max_cycles
def checksum_xcel_vrtl(words):
assert len(words) == 8
# Create a simulator using RTL accelerator
dut = ChecksumXcelRTL()
dut.elaborate()
# Translate the checksum unit and import it back in using the yosys
# backend
dut.set_metadata(YosysTranslationImportPass.enable, True)
dut = YosysTranslationImportPass()(dut)
# Create a simulator
dut.elaborate()
dut.apply(DefaultPassGroup())
dut.sim_reset()
reqs, _ = mk_xcel_transaction(words)
for req in reqs:
# Wait until xcel is ready to accept a request
dut.xcel.resp.rdy @= 1
while not dut.xcel.req.rdy:
dut.xcel.req.en @= 0
dut.sim_tick()
# Send a request
dut.xcel.req.en @= 1
dut.xcel.req.msg @= req
dut.sim_tick()
# Wait for response
while not dut.xcel.resp.en:
dut.xcel.req.en @= 0
dut.sim_tick()
# Get the response message
resp_data = dut.xcel.resp.msg.data
dut.sim_tick()
return resp_data
def run_sim( s, th, max_cycles=1000 ):
s.vcd_file_name = s.__class__.cmdline_opts["dump_vcd"]
# Check command line arguments for vcd dumping
if s.vcd_file_name:
th.dump_vcd = True
th.vcd_file_name = "translated."+s.vcd_file_name
# Translate the DUT and import it back in using the yosys backend.
th.elaborate()
th.dut.set_metadata( YosysTranslationImportPass.enable, True )
# ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''
# Apply the translation-import and simulation passes
# ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''\/
th = YosysTranslationImportPass()( th )
th.apply( DefaultPassGroup() )
# ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''/\
th.sim_reset()
# Tick the simulator
while not th.done() and th.sim_cycle_count() < max_cycles:
th.sim_tick()
# Check timeout
assert th.sim_cycle_count() < max_cycles
def run_sim(s, th, gen_test, max_cycles=10000):
th.elaborate()
# Assemble the program
mem_image = assemble(gen_test())
# Load the program into memory
th.load(mem_image)
# Translate the processor and import it back in
from pymtl3.passes.backends.yosys import YosysTranslationImportPass
th.proc.set_metadata(YosysTranslationImportPass.enable, True)
th = YosysTranslationImportPass()(th)
# Create a simulator and run simulation
th.apply(DefaultPassGroup(print_line_trace=True))
th.sim_reset()
while not th.done() and th.sim_cycle_count() < max_cycles:
th.sim_tick()
# Force a test failure if we timed out
assert th.sim_cycle_count() < max_cycles