def test_L1_wire_index(): a = CaseConnectInToWireComp.DUT() a.elaborate() a.apply(StructuralRTLIRGenL1Pass(gen_connections(a))) connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections) comp = sexp.CurComp(a, 's') assert connections[0] == \ (sexp.WireIndex(sexp.CurCompAttr(comp, 'wire_'), 2), sexp.CurCompAttr(comp, 'out'))
def test_L1_wire_index(): class A(dsl.Component): def construct(s): s.in_ = [dsl.InPort(Bits32) for _ in range(5)] s.wire = [dsl.Wire(Bits32) for _ in range(5)] s.out = dsl.OutPort(Bits32) dsl.connect(s.wire[2], s.out) for i in range(5): dsl.connect(s.wire[i], s.in_[i]) a = A() a.elaborate() a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a))) ns = a._pass_structural_rtlir_gen comp = sexp.CurComp(a, 's') assert ns.connections[0] == \ (sexp.WireIndex(sexp.CurCompAttr(comp, 'wire'), 2), sexp.CurCompAttr(comp, 'out'))