def local_do_test( m ): m.elaborate() YosysStructuralTranslatorL1.is_sverilog_reserved = is_sverilog_reserved tr = YosysStructuralTranslatorL1( m ) tr.clear( m ) tr.translate_structural( m ) ports = tr.structural.decl_ports[m] wires = tr.structural.decl_wires[m] conns = tr.structural.connections[m] check_eq( ports["port_decls"], m._ref_ports_port_yosys[m] ) check_eq( ports["wire_decls"], m._ref_ports_wire_yosys[m] ) check_eq( ports["connections"], m._ref_ports_conn_yosys[m] ) check_eq( wires, m._ref_wires_yosys[m] ) check_eq( conns, m._ref_conns_yosys[m] )
def local_do_test(m):
m.elaborate()
YosysStructuralTranslatorL4.is_sverilog_reserved = is_sverilog_reserved
tr = YosysStructuralTranslatorL4(m)
tr.clear(m)
tr.translate_structural(m)
comps = tr.structural.decl_subcomps[m]
check_eq(comps["port_decls"], m._ref_comps_port_yosys[m])
check_eq(comps["wire_decls"], m._ref_comps_wire_yosys[m])
check_eq(comps["connections"], m._ref_comps_conn_yosys[m])
def local_do_test(m):
m.elaborate()
tr = SVTranslator(m)
tr.translate(m)
check_eq(tr.hierarchy.src, m._ref_src)
