def basic_test(board_id, file):
with ConnectHelper.session_with_chosen_probe(
unique_id=board_id, **get_session_options()) as session:
board = session.board
addr = 0
size = 0
f = None
binary_file = "l1_"
if file is None:
binary_file = os.path.join(parentdir, 'binaries',
board.test_binary)
else:
binary_file = file
print("binary file: %s" % binary_file)
memory_map = board.target.get_memory_map()
ram_region = memory_map.get_first_region_of_type(MemoryType.RAM)
rom_region = memory_map.get_boot_memory()
addr = ram_region.start
size = 0x502
addr_bin = rom_region.start
addr_flash = rom_region.start + rom_region.length // 2
target = board.target
flash = rom_region.flash
print("\n\n------ GET Unique ID ------")
print("Unique ID: %s" % board.unique_id)
print("\n\n------ TEST READ / WRITE CORE REGISTER ------")
pc = target.read_core_register('pc')
print("initial pc: 0x%X" % target.read_core_register('pc'))
# write in pc dummy value
target.write_core_register('pc', 0x3D82)
print("now pc: 0x%X" % target.read_core_register('pc'))
# write initial pc value
target.write_core_register('pc', pc)
print("initial pc value rewritten: 0x%X" %
target.read_core_register('pc'))
msp = target.read_core_register('msp')
psp = target.read_core_register('psp')
print("MSP = 0x%08x; PSP = 0x%08x" % (msp, psp))
control = target.read_core_register('control')
faultmask = target.read_core_register('faultmask')
basepri = target.read_core_register('basepri')
primask = target.read_core_register('primask')
print(
"CONTROL = 0x%02x; FAULTMASK = 0x%02x; BASEPRI = 0x%02x; PRIMASK = 0x%02x"
% (control, faultmask, basepri, primask))
target.write_core_register('primask', 1)
newPrimask = target.read_core_register('primask')
print("New PRIMASK = 0x%02x" % newPrimask)
target.write_core_register('primask', primask)
newPrimask = target.read_core_register('primask')
print("Restored PRIMASK = 0x%02x" % newPrimask)
if target.has_fpu:
s0 = target.read_core_register('s0')
print("S0 = %g (0x%08x)" % (s0, float32_to_u32(s0)))
target.write_core_register('s0', math.pi)
newS0 = target.read_core_register('s0')
print("New S0 = %g (0x%08x)" % (newS0, float32_to_u32(newS0)))
target.write_core_register('s0', s0)
newS0 = target.read_core_register('s0')
print("Restored S0 = %g (0x%08x)" % (newS0, float32_to_u32(newS0)))
print("\n\n------ TEST HALT / RESUME ------")
print("resume")
target.resume()
sleep(0.2)
print("halt")
target.halt()
print("HALT: pc: 0x%X" % target.read_core_register('pc'))
sleep(0.2)
print("\n\n------ TEST STEP ------")
print("reset and halt")
target.reset_and_halt()
currentPC = target.read_core_register('pc')
print("HALT: pc: 0x%X" % currentPC)
sleep(0.2)
for i in range(4):
print("step")
target.step()
newPC = target.read_core_register('pc')
print("STEP: pc: 0x%X" % newPC)
currentPC = newPC
sleep(0.2)
print("\n\n------ TEST READ / WRITE MEMORY ------")
target.halt()
print("READ32/WRITE32")
val = randrange(0, 0xffffffff)
print("write32 0x%X at 0x%X" % (val, addr))
target.write_memory(addr, val)
res = target.read_memory(addr)
print("read32 at 0x%X: 0x%X" % (addr, res))
if res != val:
print("ERROR in READ/WRITE 32")
print("\nREAD16/WRITE16")
val = randrange(0, 0xffff)
print("write16 0x%X at 0x%X" % (val, addr + 2))
target.write_memory(addr + 2, val, 16)
res = target.read_memory(addr + 2, 16)
print("read16 at 0x%X: 0x%X" % (addr + 2, res))
if res != val:
print("ERROR in READ/WRITE 16")
print("\nREAD8/WRITE8")
val = randrange(0, 0xff)
print("write8 0x%X at 0x%X" % (val, addr + 1))
target.write_memory(addr + 1, val, 8)
res = target.read_memory(addr + 1, 8)
print("read8 at 0x%X: 0x%X" % (addr + 1, res))
if res != val:
print("ERROR in READ/WRITE 8")
print("\n\n------ TEST READ / WRITE MEMORY BLOCK ------")
data = [randrange(1, 50) for x in range(size)]
target.write_memory_block8(addr, data)
block = target.read_memory_block8(addr, size)
error = False
for i in range(len(block)):
if (block[i] != data[i]):
error = True
print("ERROR: 0x%X, 0x%X, 0x%X!!!" %
((addr + i), block[i], data[i]))
if error:
print("TEST FAILED")
else:
print("TEST PASSED")
print("\n\n------ TEST RESET ------")
target.reset()
sleep(0.1)
target.halt()
for i in range(5):
target.step()
print("pc: 0x%X" % target.read_core_register('pc'))
print("\n\n------ TEST PROGRAM/ERASE PAGE ------")
# Fill 3 pages with 0x55
page_size = flash.get_page_info(addr_flash).size
fill = [0x55] * page_size
for i in range(0, 3):
address = addr_flash + page_size * i
# Test only supports a location with 3 aligned
# pages of the same size
current_page_size = flash.get_page_info(addr_flash).size
assert page_size == current_page_size
assert address % current_page_size == 0
flash.init(flash.Operation.ERASE)
flash.erase_page(address)
flash.uninit()
flash.init(flash.Operation.PROGRAM)
flash.program_page(address, fill)
flash.uninit()
# Erase the middle page
flash.init(flash.Operation.ERASE)
flash.erase_page(addr_flash + page_size)
flash.cleanup()
# Verify the 1st and 3rd page were not erased, and that the 2nd page is fully erased
data = target.read_memory_block8(addr_flash, page_size * 3)
expected = fill + [0xFF] * page_size + fill
if data == expected:
print("TEST PASSED")
else:
print("TEST FAILED")
print("\n\n----- FLASH NEW BINARY -----")
FileProgrammer(session).program(binary_file, base_address=addr_bin)
target.reset()
def cortex_test(board_id):
with ConnectHelper.session_with_chosen_probe(
board_id=board_id, **get_session_options()) as session:
board = session.board
target_type = board.target_type
binary_file = os.path.join(parentdir, 'binaries', board.test_binary)
test_params = get_target_test_params(session)
test_clock = test_params['test_clock']
addr_invalid = 0x3E000000 # Last 16MB of ARM SRAM region - typically empty
expect_invalid_access_to_fail = test_params['error_on_invalid_access']
memory_map = board.target.get_memory_map()
ram_region = memory_map.get_first_region_of_type(MemoryType.RAM)
rom_region = memory_map.get_boot_memory()
addr = ram_region.start
size = 0x502
addr_bin = rom_region.start
target = board.target
probe = session.probe
probe.set_clock(test_clock)
test_pass_count = 0
test_count = 0
result = CortexTestResult()
debugContext = target.get_target_context()
gdbFacade = GDBDebugContextFacade(debugContext)
print("\n\n----- FLASH NEW BINARY BEFORE TEST -----")
FileProgrammer(session).program(binary_file, base_address=addr_bin)
# Let the target run for a bit so it
# can initialize the watchdog if it needs to
target.resume()
sleep(0.2)
target.halt()
print("PROGRAMMING COMPLETE")
print("\n\n----- TESTING CORTEX-M PERFORMANCE -----")
test_time = test_function(session, gdbFacade.get_t_response)
result.times["get_t_response"] = test_time
print("Function get_t_response time: %f" % test_time)
# Step
test_time = test_function(session, target.step)
result.times["step"] = test_time
print("Function step time: %f" % test_time)
# Breakpoint
def set_remove_breakpoint():
target.set_breakpoint(0)
target.remove_breakpoint(0)
test_time = test_function(session, set_remove_breakpoint)
result.times["bp_add_remove"] = test_time
print("Add and remove breakpoint: %f" % test_time)
# get_register_context
test_time = test_function(session, gdbFacade.get_register_context)
result.times["get_reg_context"] = test_time
print("Function get_register_context: %f" % test_time)
# set_register_context
context = gdbFacade.get_register_context()
def set_register_context():
gdbFacade.set_register_context(context)
test_time = test_function(session, set_register_context)
result.times["set_reg_context"] = test_time
print("Function set_register_context: %f" % test_time)
# Run / Halt
def run_halt():
target.resume()
target.halt()
test_time = test_function(session, run_halt)
result.times["run_halt"] = test_time
print("Resume and halt: %f" % test_time)
# GDB stepping
def simulate_step():
target.step()
gdbFacade.get_t_response()
target.set_breakpoint(0)
target.resume()
target.halt()
gdbFacade.get_t_response()
target.remove_breakpoint(0)
test_time = test_function(session, simulate_step)
result.times["gdb_step"] = test_time
print("Simulated GDB step: %f" % test_time)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Reset Types ------")
def reset_methods(fnc):
print("Hardware reset")
fnc(reset_type=Target.ResetType.HW)
print("Hardware reset (default=HW)")
target.selected_core.default_reset_type = Target.ResetType.HW
fnc(reset_type=None)
print("Software reset (default=SYSRESETREQ)")
target.selected_core.default_reset_type = Target.ResetType.SW_SYSRESETREQ
fnc(reset_type=None)
print("Software reset (default=VECTRESET)")
target.selected_core.default_reset_type = Target.ResetType.SW_VECTRESET
fnc(reset_type=None)
print("Software reset (default=emulated)")
target.selected_core.default_reset_type = Target.ResetType.SW_EMULATED
fnc(reset_type=None)
print("(Default) Software reset (SYSRESETREQ)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSRESETREQ
fnc(reset_type=Target.ResetType.SW)
print("(Default) Software reset (VECTRESET)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_VECTRESET
fnc(reset_type=Target.ResetType.SW)
print("(Default) Software reset (emulated)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_EMULATED
fnc(reset_type=Target.ResetType.SW)
print("Software reset (option=default)")
target.selected_core.default_reset_type = Target.ResetType.SW
target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSRESETREQ
session.options['reset_type'] = 'default'
fnc(reset_type=None)
print("Software reset (option=hw)")
session.options['reset_type'] = 'hw'
fnc(reset_type=None)
print("Software reset (option=sw)")
session.options['reset_type'] = 'sw'
fnc(reset_type=None)
print("Software reset (option=sw_sysresetreq)")
session.options['reset_type'] = 'sw_sysresetreq'
fnc(reset_type=None)
print("Software reset (option=sw_vectreset)")
session.options['reset_type'] = 'sw_vectreset'
fnc(reset_type=None)
print("Software reset (option=sw_emulated)")
session.options['reset_type'] = 'sw_emulated'
fnc(reset_type=None)
reset_methods(target.reset)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Reset Halt ------")
reset_methods(target.reset_and_halt)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Register Read/Write ------")
print("Reading r0")
val = target.read_core_register('r0')
origR0 = val
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == rawVal:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Writing r0")
target.write_core_register('r0', 0x12345678)
val = target.read_core_register('r0')
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == 0x12345678 and rawVal == 0x12345678:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Raw writing r0")
target.write_core_register_raw('r0', 0x87654321)
val = target.read_core_register('r0')
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == 0x87654321 and rawVal == 0x87654321:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Read/write r0, r1, r2, r3")
origRegs = target.read_core_registers_raw(['r0', 'r1', 'r2', 'r3'])
target.write_core_registers_raw(['r0', 'r1', 'r2', 'r3'], [1, 2, 3, 4])
vals = target.read_core_registers_raw(['r0', 'r1', 'r2', 'r3'])
passed = vals[0] == 1 and vals[1] == 2 and vals[2] == 3 and vals[3] == 4
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
# Restore regs
origRegs[0] = origR0
target.write_core_registers_raw(['r0', 'r1', 'r2', 'r3'], origRegs)
if target.selected_core.has_fpu:
print("Reading s0")
val = target.read_core_register('s0')
rawVal = target.read_core_register_raw('s0')
origRawS0 = rawVal
passed = isinstance(val, float) and isinstance(rawVal, int) \
and float32_to_u32(val) == rawVal
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Writing s0")
target.write_core_register('s0', math.pi)
val = target.read_core_register('s0')
rawVal = target.read_core_register_raw('s0')
passed = float_compare(val, math.pi) and float_compare(
u32_to_float32(rawVal), math.pi)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (%f==%f, 0x%08x->%f)" %
(val, math.pi, rawVal, u32_to_float32(rawVal)))
print("Raw writing s0")
x = float32_to_u32(32.768)
target.write_core_register_raw('s0', x)
val = target.read_core_register('s0')
passed = float_compare(val, 32.768)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (%f==%f)" % (val, 32.768))
print("Read/write s0, s1")
_1p1 = float32_to_u32(1.1)
_2p2 = float32_to_u32(2.2)
origRegs = target.read_core_registers_raw(['s0', 's1'])
target.write_core_registers_raw(['s0', 's1'], [_1p1, _2p2])
vals = target.read_core_registers_raw(['s0', 's1'])
s0 = target.read_core_register('s0')
s1 = target.read_core_register('s1')
passed = vals[0] == _1p1 and float_compare(s0, 1.1) \
and vals[1] == _2p2 and float_compare(s1, 2.2)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (0x%08x==0x%08x, %f==%f, 0x%08x==0x%08x, %f==%f)" \
% (vals[0], _1p1, s0, 1.1, vals[1], _2p2, s1, 2.2))
# Restore s0
origRegs[0] = origRawS0
target.write_core_registers_raw(['s0', 's1'], origRegs)
print("\n\n------ Testing Invalid Memory Access Recovery ------")
memory_access_pass = True
try:
print("reading 0x1000 bytes at invalid address 0x%08x" %
addr_invalid)
target.read_memory_block8(addr_invalid, 0x1000)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
try:
print("reading 0x1000 bytes at invalid address 0x%08x" %
(addr_invalid + 1))
target.read_memory_block8(addr_invalid + 1, 0x1000)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [0x00] * 0x1000
try:
print("writing 0x%08x bytes at invalid address 0x%08x" %
(len(data), addr_invalid))
target.write_memory_block8(addr_invalid, data)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault!")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [0x00] * 0x1000
try:
print("writing 0x%08x bytes at invalid address 0x%08x" %
(len(data), addr_invalid + 1))
target.write_memory_block8(addr_invalid + 1, data)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault!")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [randrange(0, 255) for x in range(size)]
print("r/w 0x%08x bytes at 0x%08x" % (size, addr))
target.write_memory_block8(addr, data)
block = target.read_memory_block8(addr, size)
if same(data, block):
print(" Aligned access pass")
else:
print(" Memory read does not match memory written")
memory_access_pass = False
data = [randrange(0, 255) for x in range(size)]
print("r/w 0x%08x bytes at 0x%08x" % (size, addr + 1))
target.write_memory_block8(addr + 1, data)
block = target.read_memory_block8(addr + 1, size)
if same(data, block):
print(" Unaligned access pass")
else:
print(" Unaligned memory read does not match memory written")
memory_access_pass = False
test_count += 1
if memory_access_pass:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("\n\n------ Testing Software Breakpoints ------")
test_passed = True
orig8x2 = target.read_memory_block8(addr, 2)
orig8 = target.read8(addr)
orig16 = target.read16(addr & ~1)
orig32 = target.read32(addr & ~3)
origAligned32 = target.read_memory_block32(addr & ~3, 1)
def test_filters():
test_passed = True
filtered = target.read_memory_block8(addr, 2)
if same(orig8x2, filtered):
print("2 byte unaligned passed")
else:
print("2 byte unaligned failed (read %x-%x, expected %x-%x)" %
(filtered[0], filtered[1], orig8x2[0], orig8x2[1]))
test_passed = False
for now in (True, False):
filtered = target.read8(addr, now)
if not now:
filtered = filtered()
if filtered == orig8:
print("8-bit passed [now=%s]" % now)
else:
print("8-bit failed [now=%s] (read %x, expected %x)" %
(now, filtered, orig8))
test_passed = False
filtered = target.read16(addr & ~1, now)
if not now:
filtered = filtered()
if filtered == orig16:
print("16-bit passed [now=%s]" % now)
else:
print("16-bit failed [now=%s] (read %x, expected %x)" %
(now, filtered, orig16))
test_passed = False
filtered = target.read32(addr & ~3, now)
if not now:
filtered = filtered()
if filtered == orig32:
print("32-bit passed [now=%s]" % now)
else:
print("32-bit failed [now=%s] (read %x, expected %x)" %
(now, filtered, orig32))
test_passed = False
filtered = target.read_memory_block32(addr & ~3, 1)
if same(filtered, origAligned32):
print("32-bit aligned passed")
else:
print("32-bit aligned failed (read %x, expected %x)" %
(filtered[0], origAligned32[0]))
test_passed = False
return test_passed
print("Installed software breakpoint at 0x%08x" % addr)
target.set_breakpoint(addr, Target.BREAKPOINT_SW)
test_passed = test_filters() and test_passed
print("Removed software breakpoint")
target.remove_breakpoint(addr)
test_passed = test_filters() and test_passed
test_count += 1
if test_passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
target.reset()
result.passed = test_count == test_pass_count
return result
def test_float32beToU32be(self):
assert float32_to_u32(5.690456613903524e-28) == 0x012345678
def cortex_test(board_id):
with ConnectHelper.session_with_chosen_probe(unique_id=board_id, **get_session_options()) as session:
board = session.board
target_type = board.target_type
binary_file = os.path.join(parentdir, 'binaries', board.test_binary)
test_params = get_target_test_params(session)
test_clock = test_params['test_clock']
addr_invalid = 0x3E000000 # Last 16MB of ARM SRAM region - typically empty
expect_invalid_access_to_fail = test_params['error_on_invalid_access']
memory_map = board.target.get_memory_map()
ram_region = memory_map.get_first_region_of_type(MemoryType.RAM)
rom_region = memory_map.get_boot_memory()
addr = ram_region.start
size = 0x502
addr_bin = rom_region.start
target = board.target
probe = session.probe
probe.set_clock(test_clock)
test_pass_count = 0
test_count = 0
result = CortexTestResult()
debugContext = target.get_target_context()
gdbFacade = GDBDebugContextFacade(debugContext)
print("\n\n----- FLASH NEW BINARY BEFORE TEST -----")
FileProgrammer(session).program(binary_file, base_address=addr_bin)
# Let the target run for a bit so it
# can initialize the watchdog if it needs to
target.resume()
sleep(0.2)
target.halt()
print("PROGRAMMING COMPLETE")
print("\n\n----- TESTING CORTEX-M PERFORMANCE -----")
test_time = test_function(session, gdbFacade.get_t_response)
result.times["get_t_response"] = test_time
print("Function get_t_response time: %f" % test_time)
# Step
test_time = test_function(session, target.step)
result.times["step"] = test_time
print("Function step time: %f" % test_time)
# Breakpoint
def set_remove_breakpoint():
target.set_breakpoint(0)
target.remove_breakpoint(0)
test_time = test_function(session, set_remove_breakpoint)
result.times["bp_add_remove"] = test_time
print("Add and remove breakpoint: %f" % test_time)
# get_register_context
test_time = test_function(session, gdbFacade.get_register_context)
result.times["get_reg_context"] = test_time
print("Function get_register_context: %f" % test_time)
# set_register_context
context = gdbFacade.get_register_context()
def set_register_context():
gdbFacade.set_register_context(context)
test_time = test_function(session, set_register_context)
result.times["set_reg_context"] = test_time
print("Function set_register_context: %f" % test_time)
# Run / Halt
def run_halt():
target.resume()
target.halt()
test_time = test_function(session, run_halt)
result.times["run_halt"] = test_time
print("Resume and halt: %f" % test_time)
# GDB stepping
def simulate_step():
target.step()
gdbFacade.get_t_response()
target.set_breakpoint(0)
target.resume()
target.halt()
gdbFacade.get_t_response()
target.remove_breakpoint(0)
test_time = test_function(session, simulate_step)
result.times["gdb_step"] = test_time
print("Simulated GDB step: %f" % test_time)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Reset Types ------")
def reset_methods(fnc):
print("Hardware reset")
fnc(reset_type=Target.ResetType.HW)
print("Hardware reset (default=HW)")
target.selected_core.default_reset_type = Target.ResetType.HW
fnc(reset_type=None)
print("Software reset (default=SYSRESETREQ)")
target.selected_core.default_reset_type = Target.ResetType.SW_SYSRESETREQ
fnc(reset_type=None)
print("Software reset (default=VECTRESET)")
target.selected_core.default_reset_type = Target.ResetType.SW_VECTRESET
fnc(reset_type=None)
print("Software reset (default=emulated)")
target.selected_core.default_reset_type = Target.ResetType.SW_EMULATED
fnc(reset_type=None)
print("(Default) Software reset (SYSRESETREQ)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSRESETREQ
fnc(reset_type=Target.ResetType.SW)
print("(Default) Software reset (VECTRESET)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_VECTRESET
fnc(reset_type=Target.ResetType.SW)
print("(Default) Software reset (emulated)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_EMULATED
fnc(reset_type=Target.ResetType.SW)
print("Software reset (option=default)")
target.selected_core.default_reset_type = Target.ResetType.SW
target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSRESETREQ
session.options['reset_type'] = 'default'
fnc(reset_type=None)
print("Software reset (option=hw)")
session.options['reset_type'] = 'hw'
fnc(reset_type=None)
print("Software reset (option=sw)")
session.options['reset_type'] = 'sw'
fnc(reset_type=None)
print("Software reset (option=sw_sysresetreq)")
session.options['reset_type'] = 'sw_sysresetreq'
fnc(reset_type=None)
print("Software reset (option=sw_vectreset)")
session.options['reset_type'] = 'sw_vectreset'
fnc(reset_type=None)
print("Software reset (option=sw_emulated)")
session.options['reset_type'] = 'sw_emulated'
fnc(reset_type=None)
reset_methods(target.reset)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Reset Halt ------")
reset_methods(target.reset_and_halt)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Register Read/Write ------")
print("Reading r0")
val = target.read_core_register('r0')
origR0 = val
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == rawVal:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Writing r0")
target.write_core_register('r0', 0x12345678)
val = target.read_core_register('r0')
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == 0x12345678 and rawVal == 0x12345678:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Raw writing r0")
target.write_core_register_raw('r0', 0x87654321)
val = target.read_core_register('r0')
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == 0x87654321 and rawVal == 0x87654321:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Read/write r0, r1, r2, r3")
origRegs = target.read_core_registers_raw(['r0', 'r1', 'r2', 'r3'])
target.write_core_registers_raw(['r0', 'r1', 'r2', 'r3'], [1, 2, 3, 4])
vals = target.read_core_registers_raw(['r0', 'r1', 'r2', 'r3'])
passed = vals[0] == 1 and vals[1] == 2 and vals[2] == 3 and vals[3] == 4
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
# Restore regs
origRegs[0] = origR0
target.write_core_registers_raw(['r0', 'r1', 'r2', 'r3'], origRegs)
if target.selected_core.has_fpu:
print("Reading s0")
val = target.read_core_register('s0')
rawVal = target.read_core_register_raw('s0')
origRawS0 = rawVal
passed = isinstance(val, float) and isinstance(rawVal, int) \
and float32_to_u32(val) == rawVal
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Writing s0")
target.write_core_register('s0', math.pi)
val = target.read_core_register('s0')
rawVal = target.read_core_register_raw('s0')
passed = float_compare(val, math.pi) and float_compare(u32_to_float32(rawVal), math.pi)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (%f==%f, 0x%08x->%f)" % (val, math.pi, rawVal, u32_to_float32(rawVal)))
print("Raw writing s0")
x = float32_to_u32(32.768)
target.write_core_register_raw('s0', x)
val = target.read_core_register('s0')
passed = float_compare(val, 32.768)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (%f==%f)" % (val, 32.768))
print("Read/write s0, s1")
_1p1 = float32_to_u32(1.1)
_2p2 = float32_to_u32(2.2)
origRegs = target.read_core_registers_raw(['s0', 's1'])
target.write_core_registers_raw(['s0', 's1'], [_1p1, _2p2])
vals = target.read_core_registers_raw(['s0', 's1'])
s0 = target.read_core_register('s0')
s1 = target.read_core_register('s1')
passed = vals[0] == _1p1 and float_compare(s0, 1.1) \
and vals[1] == _2p2 and float_compare(s1, 2.2)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (0x%08x==0x%08x, %f==%f, 0x%08x==0x%08x, %f==%f)" \
% (vals[0], _1p1, s0, 1.1, vals[1], _2p2, s1, 2.2))
# Restore s0
origRegs[0] = origRawS0
target.write_core_registers_raw(['s0', 's1'], origRegs)
print("\n\n------ Testing Invalid Memory Access Recovery ------")
memory_access_pass = True
try:
print("reading 0x1000 bytes at invalid address 0x%08x" % addr_invalid)
target.read_memory_block8(addr_invalid, 0x1000)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
try:
print("reading 0x1000 bytes at invalid address 0x%08x" % (addr_invalid + 1))
target.read_memory_block8(addr_invalid + 1, 0x1000)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [0x00] * 0x1000
try:
print("writing 0x%08x bytes at invalid address 0x%08x" % (len(data), addr_invalid))
target.write_memory_block8(addr_invalid, data)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault!")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [0x00] * 0x1000
try:
print("writing 0x%08x bytes at invalid address 0x%08x" % (len(data), addr_invalid + 1))
target.write_memory_block8(addr_invalid + 1, data)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault!")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [randrange(0, 255) for x in range(size)]
print("r/w 0x%08x bytes at 0x%08x" % (size, addr))
target.write_memory_block8(addr, data)
block = target.read_memory_block8(addr, size)
if same(data, block):
print(" Aligned access pass")
else:
print(" Memory read does not match memory written")
memory_access_pass = False
data = [randrange(0, 255) for x in range(size)]
print("r/w 0x%08x bytes at 0x%08x" % (size, addr + 1))
target.write_memory_block8(addr + 1, data)
block = target.read_memory_block8(addr + 1, size)
if same(data, block):
print(" Unaligned access pass")
else:
print(" Unaligned memory read does not match memory written")
memory_access_pass = False
test_count += 1
if memory_access_pass:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("\n\n------ Testing Software Breakpoints ------")
test_passed = True
orig8x2 = target.read_memory_block8(addr, 2)
orig8 = target.read8(addr)
orig16 = target.read16(addr & ~1)
orig32 = target.read32(addr & ~3)
origAligned32 = target.read_memory_block32(addr & ~3, 1)
def test_filters():
test_passed = True
filtered = target.read_memory_block8(addr, 2)
if same(orig8x2, filtered):
print("2 byte unaligned passed")
else:
print("2 byte unaligned failed (read %x-%x, expected %x-%x)" % (filtered[0], filtered[1], orig8x2[0], orig8x2[1]))
test_passed = False
for now in (True, False):
filtered = target.read8(addr, now)
if not now:
filtered = filtered()
if filtered == orig8:
print("8-bit passed [now=%s]" % now)
else:
print("8-bit failed [now=%s] (read %x, expected %x)" % (now, filtered, orig8))
test_passed = False
filtered = target.read16(addr & ~1, now)
if not now:
filtered = filtered()
if filtered == orig16:
print("16-bit passed [now=%s]" % now)
else:
print("16-bit failed [now=%s] (read %x, expected %x)" % (now, filtered, orig16))
test_passed = False
filtered = target.read32(addr & ~3, now)
if not now:
filtered = filtered()
if filtered == orig32:
print("32-bit passed [now=%s]" % now)
else:
print("32-bit failed [now=%s] (read %x, expected %x)" % (now, filtered, orig32))
test_passed = False
filtered = target.read_memory_block32(addr & ~3, 1)
if same(filtered, origAligned32):
print("32-bit aligned passed")
else:
print("32-bit aligned failed (read %x, expected %x)" % (filtered[0], origAligned32[0]))
test_passed = False
return test_passed
print("Installed software breakpoint at 0x%08x" % addr)
target.set_breakpoint(addr, Target.BREAKPOINT_SW)
test_passed = test_filters() and test_passed
print("Removed software breakpoint")
target.remove_breakpoint(addr)
test_passed = test_filters() and test_passed
test_count += 1
if test_passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
target.reset()
result.passed = test_count == test_pass_count
return result
def test_float32beToU32be(self):
assert float32_to_u32(5.690456613903524e-28) == 0x012345678
def basic_test(board_id, file):
with ConnectHelper.session_with_chosen_probe(unique_id=board_id, **get_session_options()) as session:
board = session.board
addr = 0
size = 0
f = None
binary_file = "l1_"
if file is None:
binary_file = os.path.join(parentdir, 'binaries', board.test_binary)
else:
binary_file = file
print("binary file: %s" % binary_file)
memory_map = board.target.get_memory_map()
ram_region = memory_map.get_first_region_of_type(MemoryType.RAM)
rom_region = memory_map.get_boot_memory()
addr = ram_region.start
size = 0x502
addr_bin = rom_region.start
addr_flash = rom_region.start + rom_region.length // 2
target = board.target
flash = rom_region.flash
print("\n\n------ GET Unique ID ------")
print("Unique ID: %s" % board.unique_id)
print("\n\n------ TEST READ / WRITE CORE REGISTER ------")
pc = target.read_core_register('pc')
print("initial pc: 0x%X" % target.read_core_register('pc'))
# write in pc dummy value
target.write_core_register('pc', 0x3D82)
print("now pc: 0x%X" % target.read_core_register('pc'))
# write initial pc value
target.write_core_register('pc', pc)
print("initial pc value rewritten: 0x%X" % target.read_core_register('pc'))
msp = target.read_core_register('msp')
psp = target.read_core_register('psp')
print("MSP = 0x%08x; PSP = 0x%08x" % (msp, psp))
control = target.read_core_register('control')
faultmask = target.read_core_register('faultmask')
basepri = target.read_core_register('basepri')
primask = target.read_core_register('primask')
print("CONTROL = 0x%02x; FAULTMASK = 0x%02x; BASEPRI = 0x%02x; PRIMASK = 0x%02x" % (control, faultmask, basepri, primask))
target.write_core_register('primask', 1)
newPrimask = target.read_core_register('primask')
print("New PRIMASK = 0x%02x" % newPrimask)
target.write_core_register('primask', primask)
newPrimask = target.read_core_register('primask')
print("Restored PRIMASK = 0x%02x" % newPrimask)
if target.has_fpu:
s0 = target.read_core_register('s0')
print("S0 = %g (0x%08x)" % (s0, float32_to_u32(s0)))
target.write_core_register('s0', math.pi)
newS0 = target.read_core_register('s0')
print("New S0 = %g (0x%08x)" % (newS0, float32_to_u32(newS0)))
target.write_core_register('s0', s0)
newS0 = target.read_core_register('s0')
print("Restored S0 = %g (0x%08x)" % (newS0, float32_to_u32(newS0)))
print("\n\n------ TEST HALT / RESUME ------")
print("resume")
target.resume()
sleep(0.2)
print("halt")
target.halt()
print("HALT: pc: 0x%X" % target.read_core_register('pc'))
sleep(0.2)
print("\n\n------ TEST STEP ------")
print("reset and halt")
target.reset_stop_on_reset()
currentPC = target.read_core_register('pc')
print("HALT: pc: 0x%X" % currentPC)
sleep(0.2)
for i in range(4):
print("step")
target.step()
newPC = target.read_core_register('pc')
print("STEP: pc: 0x%X" % newPC)
currentPC = newPC
sleep(0.2)
print("\n\n------ TEST READ / WRITE MEMORY ------")
target.halt()
print("READ32/WRITE32")
val = randrange(0, 0xffffffff)
print("write32 0x%X at 0x%X" % (val, addr))
target.write_memory(addr, val)
res = target.read_memory(addr)
print("read32 at 0x%X: 0x%X" % (addr, res))
if res != val:
print("ERROR in READ/WRITE 32")
print("\nREAD16/WRITE16")
val = randrange(0, 0xffff)
print("write16 0x%X at 0x%X" % (val, addr + 2))
target.write_memory(addr + 2, val, 16)
res = target.read_memory(addr + 2, 16)
print("read16 at 0x%X: 0x%X" % (addr + 2, res))
if res != val:
print("ERROR in READ/WRITE 16")
print("\nREAD8/WRITE8")
val = randrange(0, 0xff)
print("write8 0x%X at 0x%X" % (val, addr + 1))
target.write_memory(addr + 1, val, 8)
res = target.read_memory(addr + 1, 8)
print("read8 at 0x%X: 0x%X" % (addr + 1, res))
if res != val:
print("ERROR in READ/WRITE 8")
print("\n\n------ TEST READ / WRITE MEMORY BLOCK ------")
data = [randrange(1, 50) for x in range(size)]
target.write_memory_block8(addr, data)
block = target.read_memory_block8(addr, size)
error = False
for i in range(len(block)):
if (block[i] != data[i]):
error = True
print("ERROR: 0x%X, 0x%X, 0x%X!!!" % ((addr + i), block[i], data[i]))
if error:
print("TEST FAILED")
else:
print("TEST PASSED")
print("\n\n------ TEST RESET ------")
target.reset()
sleep(0.1)
target.halt()
for i in range(5):
target.step()
print("pc: 0x%X" % target.read_core_register('pc'))
print("\n\n------ TEST PROGRAM/ERASE PAGE ------")
# Fill 3 pages with 0x55
page_size = flash.get_page_info(addr_flash).size
fill = [0x55] * page_size
for i in range(0, 3):
address = addr_flash + page_size * i
# Test only supports a location with 3 aligned
# pages of the same size
current_page_size = flash.get_page_info(addr_flash).size
assert page_size == current_page_size
assert address % current_page_size == 0
flash.init(flash.Operation.ERASE)
flash.erase_page(address)
flash.uninit()
flash.init(flash.Operation.PROGRAM)
flash.program_page(address, fill)
flash.uninit()
# Erase the middle page
flash.init(flash.Operation.ERASE)
flash.erase_page(addr_flash + page_size)
flash.cleanup()
# Verify the 1st and 3rd page were not erased, and that the 2nd page is fully erased
data = target.read_memory_block8(addr_flash, page_size * 3)
expected = fill + [0xFF] * page_size + fill
if data == expected:
print("TEST PASSED")
else:
print("TEST FAILED")
print("\n\n----- FLASH NEW BINARY -----")
FileProgrammer(session).program(binary_file, base_address=addr_bin)
target.reset()
def test_hid(workspace, parent_test):
test_info = parent_test.create_subtest("HID test")
board = workspace.board
with ConnectHelper.session_with_chosen_probe(
unique_id=board.get_unique_id()) as session:
mbed_board = session.board
target = mbed_board.target
binary_file = workspace.target.bin_path
ram_region = target.memory_map.get_default_region_of_type(
MemoryType.RAM)
rom_region = target.memory_map.get_boot_memory()
addr = ram_region.start + 4
size = 0x502
addr_bin = rom_region.start
addr_flash = rom_region.start + rom_region.length // 2
flash = rom_region.flash
test_info.info("\r\n\r\n----- FLASH NEW BINARY -----")
FileProgrammer(session).program(binary_file, base_address=addr_bin)
test_info.info("\r\n\r\n------ GET Unique ID ------")
test_info.info("Unique ID: %s" % mbed_board.unique_id)
test_info.info("\r\n\r\n------ TEST READ / WRITE CORE REGISTER ------")
pc = target.read_core_register('pc')
test_info.info("initial pc: 0x%X" % target.read_core_register('pc'))
# write in pc dummy value
target.write_core_register('pc', 0x3D82)
test_info.info("now pc: 0x%X" % target.read_core_register('pc'))
# write initial pc value
target.write_core_register('pc', pc)
test_info.info("initial pc value rewritten: 0x%X" %
target.read_core_register('pc'))
msp = target.read_core_register('msp')
psp = target.read_core_register('psp')
test_info.info("MSP = 0x%08x; PSP = 0x%08x" % (msp, psp))
if 'faultmask' in target.core_registers.by_name:
control = target.read_core_register('control')
faultmask = target.read_core_register('faultmask')
basepri = target.read_core_register('basepri')
primask = target.read_core_register('primask')
test_info.info(
"CONTROL = 0x%02x; FAULTMASK = 0x%02x; BASEPRI = 0x%02x; PRIMASK = 0x%02x"
% (control, faultmask, basepri, primask))
else:
control = target.read_core_register('control')
primask = target.read_core_register('primask')
test_info.info("CONTROL = 0x%02x; PRIMASK = 0x%02x" %
(control, primask))
target.write_core_register('primask', 1)
newPrimask = target.read_core_register('primask')
test_info.info("New PRIMASK = 0x%02x" % newPrimask)
target.write_core_register('primask', primask)
newPrimask = target.read_core_register('primask')
test_info.info("Restored PRIMASK = 0x%02x" % newPrimask)
if target.selected_core.has_fpu:
s0 = target.read_core_register('s0')
test_info.info("S0 = %g (0x%08x)" % (s0, float32_to_u32(s0)))
target.write_core_register('s0', math.pi)
newS0 = target.read_core_register('s0')
test_info.info("New S0 = %g (0x%08x)" %
(newS0, float32_to_u32(newS0)))
target.write_core_register('s0', s0)
newS0 = target.read_core_register('s0')
test_info.info("Restored S0 = %g (0x%08x)" %
(newS0, float32_to_u32(newS0)))
test_info.info("\r\n\r\n------ TEST HALT / RESUME ------")
test_info.info("resume")
target.resume()
sleep(0.2)
test_info.info("halt")
target.halt()
test_info.info("HALT: pc: 0x%X" % target.read_core_register('pc'))
sleep(0.2)
test_info.info("\r\n\r\n------ TEST STEP ------")
test_info.info("reset and halt")
target.reset_and_halt()
currentPC = target.read_core_register('pc')
test_info.info("HALT: pc: 0x%X" % currentPC)
sleep(0.2)
for i in range(4):
test_info.info("step")
target.step()
newPC = target.read_core_register('pc')
test_info.info("STEP: pc: 0x%X" % newPC)
currentPC = newPC
sleep(0.2)
test_info.info("\r\n\r\n------ TEST READ / WRITE MEMORY ------")
target.halt()
test_info.info("READ32/WRITE32")
val = randrange(0, 0xffffffff)
test_info.info("write32 0x%X at 0x%X" % (val, addr))
target.write32(addr, val)
res = target.read32(addr)
test_info.info("read32 at 0x%X: 0x%X" % (addr, res))
if res != val:
test_info.failure("ERROR in READ/WRITE 32")
test_info.info("\r\nREAD16/WRITE16")
val = randrange(0, 0xffff)
test_info.info("write16 0x%X at 0x%X" % (val, addr + 2))
target.write16(addr + 2, val)
res = target.read16(addr + 2)
test_info.info("read16 at 0x%X: 0x%X" % (addr + 2, res))
if res != val:
test_info.failure("ERROR in READ/WRITE 16")
test_info.info("\r\nREAD8/WRITE8")
val = randrange(0, 0xff)
test_info.info("write8 0x%X at 0x%X" % (val, addr + 1))
target.write8(addr + 1, val)
res = target.read8(addr + 1)
test_info.info("read8 at 0x%X: 0x%X" % (addr + 1, res))
if res != val:
test_info.failure("ERROR in READ/WRITE 8")
test_info.info("\r\n\r\n------ TEST READ / WRITE MEMORY BLOCK ------")
data = [randrange(1, 50) for _ in range(size)]
target.write_memory_block8(addr, data)
block = target.read_memory_block8(addr, size)
error = False
for i in range(len(block)):
if (block[i] != data[i]):
error = True
test_info.info("ERROR: 0x%X, 0x%X, 0x%X!!!" %
((addr + i), block[i], data[i]))
if error:
test_info.failure("TEST FAILED")
else:
test_info.info("TEST PASSED")
test_info.info("\r\n\r\n------ TEST RESET ------")
target.reset()
sleep(0.1)
target.halt()
for i in range(5):
target.step()
test_info.info("pc: 0x%X" % target.read_core_register('pc'))
target.reset()
test_info.info("HID test complete")
def cortex_test(board_id):
with ConnectHelper.session_with_chosen_probe(unique_id=board_id, **get_session_options()) as session:
board = session.board
target_type = board.target_type
binary_file = get_test_binary_path(board.test_binary)
test_params = get_target_test_params(session)
test_clock = test_params['test_clock']
addr_invalid = 0x3E000000 # Last 16MB of ARM SRAM region - typically empty
expect_invalid_access_to_fail = test_params['error_on_invalid_access']
memory_map = board.target.get_memory_map()
ram_region = memory_map.get_default_region_of_type(MemoryType.RAM)
rom_region = memory_map.get_boot_memory()
addr = ram_region.start
size = 0x502
addr_bin = rom_region.start
target = board.target
probe = session.probe
probe.set_clock(test_clock)
test_pass_count = 0
test_count = 0
result = CortexTestResult()
debugContext = target.get_target_context()
gdbFacade = GDBDebugContextFacade(debugContext)
print("\n\n----- FLASH NEW BINARY BEFORE TEST -----")
FileProgrammer(session).program(binary_file, base_address=addr_bin)
# Let the target run for a bit so it
# can initialize the watchdog if it needs to
target.resume()
sleep(0.2)
target.halt()
print("PROGRAMMING COMPLETE")
print("\n\n----- TESTING CORTEX-M PERFORMANCE -----")
test_time = test_function(session, gdbFacade.get_t_response)
result.times["get_t_response"] = test_time
print("Function get_t_response time: %f" % test_time)
# Step
test_time = test_function(session, target.step)
result.times["step"] = test_time
print("Function step time: %f" % test_time)
# Breakpoint
def set_remove_breakpoint():
target.set_breakpoint(0)
target.remove_breakpoint(0)
test_time = test_function(session, set_remove_breakpoint)
result.times["bp_add_remove"] = test_time
print("Add and remove breakpoint: %f" % test_time)
# get_register_context
test_time = test_function(session, gdbFacade.get_register_context)
result.times["get_reg_context"] = test_time
print("Function get_register_context: %f" % test_time)
# set_register_context
context = gdbFacade.get_register_context()
def set_register_context():
gdbFacade.set_register_context(context)
test_time = test_function(session, set_register_context)
result.times["set_reg_context"] = test_time
print("Function set_register_context: %f" % test_time)
# Run / Halt
def run_halt():
target.resume()
target.halt()
test_time = test_function(session, run_halt)
result.times["run_halt"] = test_time
print("Resume and halt: %f" % test_time)
# GDB stepping
def simulate_step():
target.step()
gdbFacade.get_t_response()
target.set_breakpoint(0)
target.resume()
target.halt()
gdbFacade.get_t_response()
target.remove_breakpoint(0)
test_time = test_function(session, simulate_step)
result.times["gdb_step"] = test_time
print("Simulated GDB step: %f" % test_time)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Reset Types ------")
def reset_methods(fnc):
print("Hardware reset")
fnc(reset_type=Target.ResetType.HW)
print("Hardware reset (default=HW)")
target.selected_core.default_reset_type = Target.ResetType.HW
fnc(reset_type=None)
print("Software reset (default=SYSRESETREQ)")
target.selected_core.default_reset_type = Target.ResetType.SW_SYSRESETREQ
fnc(reset_type=None)
print("Software reset (default=VECTRESET)")
target.selected_core.default_reset_type = Target.ResetType.SW_VECTRESET
fnc(reset_type=None)
print("Software reset (default=emulated)")
target.selected_core.default_reset_type = Target.ResetType.SW_EMULATED
fnc(reset_type=None)
print("(Default) Software reset (SYSRESETREQ)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSRESETREQ
fnc(reset_type=Target.ResetType.SW)
print("(Default) Software reset (VECTRESET)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_VECTRESET
fnc(reset_type=Target.ResetType.SW)
print("(Default) Software reset (emulated)")
target.selected_core.default_software_reset_type = Target.ResetType.SW_EMULATED
fnc(reset_type=Target.ResetType.SW)
print("Software reset (option=default)")
target.selected_core.default_reset_type = Target.ResetType.SW
target.selected_core.default_software_reset_type = Target.ResetType.SW_SYSRESETREQ
session.options['reset_type'] = 'default'
fnc(reset_type=None)
print("Software reset (option=hw)")
session.options['reset_type'] = 'hw'
fnc(reset_type=None)
print("Software reset (option=sw)")
session.options['reset_type'] = 'sw'
fnc(reset_type=None)
print("Software reset (option=sw_sysresetreq)")
session.options['reset_type'] = 'sw_sysresetreq'
fnc(reset_type=None)
print("Software reset (option=sw_vectreset)")
session.options['reset_type'] = 'sw_vectreset'
fnc(reset_type=None)
print("Software reset (option=sw_emulated)")
session.options['reset_type'] = 'sw_emulated'
fnc(reset_type=None)
reset_methods(target.reset)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Reset Halt ------")
reset_methods(target.reset_and_halt)
# Test passes if there are no exceptions
test_pass_count += 1
test_count += 1
print("TEST PASSED")
print("\n\n------ Testing Register Read/Write ------")
print("Reading r0")
val = target.read_core_register('r0')
origR0 = val
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == rawVal:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Writing r0")
target.write_core_register('r0', 0x12345678)
val = target.read_core_register('r0')
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == 0x12345678 and rawVal == 0x12345678:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Raw writing r0")
target.write_core_register_raw('r0', 0x87654321)
val = target.read_core_register('r0')
rawVal = target.read_core_register_raw('r0')
test_count += 1
if val == 0x87654321 and rawVal == 0x87654321:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Read/write r0, r1, r2, r3")
origRegs = target.read_core_registers_raw(['r0', 'r1', 'r2', 'r3'])
target.write_core_registers_raw(['r0', 'r1', 'r2', 'r3'], [1, 2, 3, 4])
vals = target.read_core_registers_raw(['r0', 'r1', 'r2', 'r3'])
passed = vals[0] == 1 and vals[1] == 2 and vals[2] == 3 and vals[3] == 4
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
# Restore regs
origRegs[0] = origR0
target.write_core_registers_raw(['r0', 'r1', 'r2', 'r3'], origRegs)
print("Verify exception is raised while core is running")
target.resume()
try:
val = target.read_core_register('r0')
except exceptions.CoreRegisterAccessError:
passed = True
else:
passed = False
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Verify failure to write core register while running raises exception")
try:
target.write_core_register('r0', 0x1234)
except exceptions.CoreRegisterAccessError:
passed = True
else:
passed = False
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
# Resume execution.
target.halt()
if target.selected_core.has_fpu:
print("Reading s0")
val = target.read_core_register('s0')
rawVal = target.read_core_register_raw('s0')
origRawS0 = rawVal
passed = isinstance(val, float) and isinstance(rawVal, int) \
and float32_to_u32(val) == rawVal
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("Writing s0")
target.write_core_register('s0', math.pi)
val = target.read_core_register('s0')
rawVal = target.read_core_register_raw('s0')
passed = float_compare(val, math.pi) and float_compare(u32_to_float32(rawVal), math.pi)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (%f==%f, 0x%08x->%f)" % (val, math.pi, rawVal, u32_to_float32(rawVal)))
print("Raw writing s0")
x = float32_to_u32(32.768)
target.write_core_register_raw('s0', x)
val = target.read_core_register('s0')
passed = float_compare(val, 32.768)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (%f==%f)" % (val, 32.768))
print("Read/write s0, s1")
_1p1 = float32_to_u32(1.1)
_2p2 = float32_to_u32(2.2)
origRegs = target.read_core_registers_raw(['s0', 's1'])
target.write_core_registers_raw(['s0', 's1'], [_1p1, _2p2])
vals = target.read_core_registers_raw(['s0', 's1'])
s0 = target.read_core_register('s0')
s1 = target.read_core_register('s1')
passed = vals[0] == _1p1 and float_compare(s0, 1.1) \
and vals[1] == _2p2 and float_compare(s1, 2.2)
test_count += 1
if passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED (0x%08x==0x%08x, %f==%f, 0x%08x==0x%08x, %f==%f)" \
% (vals[0], _1p1, s0, 1.1, vals[1], _2p2, s1, 2.2))
# Restore s0
origRegs[0] = origRawS0
target.write_core_registers_raw(['s0', 's1'], origRegs)
print("Verify that all listed core registers can be accessed")
def test_reg_rw(r, new_value: int, test_write: bool) -> bool:
did_pass = True
try:
# Read original value.
original_val = target.read_core_register_raw(r.name)
if not test_write:
return did_pass
# Make sure the new value changes.
if new_value == original_val:
new_value = 0
# Change the value.
target.write_core_register_raw(r.name, new_value)
read_val = target.read_core_register_raw(r.name)
if read_val != new_value:
print(f"Failed to change value of register {r.name} to {new_value:#x}; read {read_val:#x}")
did_pass = False
target.write_core_register_raw(r.name, original_val)
read_val = target.read_core_register_raw(r.name)
if read_val != original_val:
print(f"Failed to restore value of register {r.name} back to original {original_val:#x}; read {read_val:#x}")
did_pass = False
except exceptions.CoreRegisterAccessError:
did_pass = False
return did_pass
reg_count = 0
passed_reg_count = 0
for r in target.selected_core.core_registers.as_set:
test_write = True
# Decide on a new value, ensuring it changes and taking into account register specifics.
r_mask = (1 << r.bitsize) - 1
if 'sp' in r.name:
r_mask &= ~0x3
elif r.name == 'pc':
r_mask &= ~0x1
elif 'xpsr' in r.name:
r_mask = 0xd0000000
elif 'control' == r.name:
# SPSEL is available on all cores.
r_mask = 0x2
elif r.name in ('primask', 'faultmask'):
r_mask = 0x1
elif r.name == 'basepri':
r_mask = 0x80
elif r.name == 'fpscr':
# v7-M bits
r_mask = 0xf7c0009f
new_value = 0xdeadbeef & r_mask
# Skip write tests on some regs:
# - combined CFBP
# - PSR variants not including XPSR
# - all _NS and _S variants
if ((r.name in ('cfbp',))
or (('psr' in r.name) and (r.name != 'xpsr'))
or ('_ns' in r.name) or ('_s' in r.name)
):
test_write = False
reg_count += 1
if test_reg_rw(r, new_value, test_write):
passed_reg_count += 1
test_count += 1
if passed_reg_count == reg_count:
test_pass_count += 1
print("TEST PASSED (%i registers)" % reg_count)
else:
print("TEST FAILED (%i registers, %i failed)" % (reg_count, reg_count - passed_reg_count))
print("\n\n------ Testing Invalid Memory Access Recovery ------")
memory_access_pass = True
try:
print("reading 0x1000 bytes at invalid address 0x%08x" % addr_invalid)
target.read_memory_block8(addr_invalid, 0x1000)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
try:
print("reading 0x1000 bytes at invalid address 0x%08x" % (addr_invalid + 1))
target.read_memory_block8(addr_invalid + 1, 0x1000)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [0x00] * 0x1000
try:
print("writing 0x%08x bytes at invalid address 0x%08x" % (len(data), addr_invalid))
target.write_memory_block8(addr_invalid, data)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault!")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [0x00] * 0x1000
try:
print("writing 0x%08x bytes at invalid address 0x%08x" % (len(data), addr_invalid + 1))
target.write_memory_block8(addr_invalid + 1, data)
target.flush()
# If no exception is thrown the tests fails except on nrf51 where invalid addresses read as 0
if expect_invalid_access_to_fail:
print(" failed to get expected fault!")
memory_access_pass = False
else:
print(" no fault as expected")
except exceptions.TransferFaultError as exc:
print(" got expected error: " + str(exc))
data = [randrange(0, 255) for x in range(size)]
print("r/w 0x%08x bytes at 0x%08x" % (size, addr))
target.write_memory_block8(addr, data)
block = target.read_memory_block8(addr, size)
if same(data, block):
print(" Aligned access pass")
else:
print(" Memory read does not match memory written")
memory_access_pass = False
data = [randrange(0, 255) for x in range(size)]
print("r/w 0x%08x bytes at 0x%08x" % (size, addr + 1))
target.write_memory_block8(addr + 1, data)
block = target.read_memory_block8(addr + 1, size)
if same(data, block):
print(" Unaligned access pass")
else:
print(" Unaligned memory read does not match memory written")
memory_access_pass = False
test_count += 1
if memory_access_pass:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("\n\n------ Testing Software Breakpoints ------")
test_passed = True
orig8x2 = target.read_memory_block8(addr, 2)
orig8 = target.read8(addr)
orig16 = target.read16(addr & ~1)
orig32 = target.read32(addr & ~3)
origAligned32 = target.read_memory_block32(addr & ~3, 1)
def test_filters():
test_passed = True
filtered = target.read_memory_block8(addr, 2)
if same(orig8x2, filtered):
print("2 byte unaligned passed")
else:
print("2 byte unaligned failed (read %x-%x, expected %x-%x)" % (filtered[0], filtered[1], orig8x2[0], orig8x2[1]))
test_passed = False
for now in (True, False):
filtered = target.read8(addr, now)
if not now:
filtered = filtered()
if filtered == orig8:
print("8-bit passed [now=%s]" % now)
else:
print("8-bit failed [now=%s] (read %x, expected %x)" % (now, filtered, orig8))
test_passed = False
filtered = target.read16(addr & ~1, now)
if not now:
filtered = filtered()
if filtered == orig16:
print("16-bit passed [now=%s]" % now)
else:
print("16-bit failed [now=%s] (read %x, expected %x)" % (now, filtered, orig16))
test_passed = False
filtered = target.read32(addr & ~3, now)
if not now:
filtered = filtered()
if filtered == orig32:
print("32-bit passed [now=%s]" % now)
else:
print("32-bit failed [now=%s] (read %x, expected %x)" % (now, filtered, orig32))
test_passed = False
filtered = target.read_memory_block32(addr & ~3, 1)
if same(filtered, origAligned32):
print("32-bit aligned passed")
else:
print("32-bit aligned failed (read %x, expected %x)" % (filtered[0], origAligned32[0]))
test_passed = False
return test_passed
print("Installed software breakpoint at 0x%08x" % addr)
target.set_breakpoint(addr, Target.BreakpointType.SW)
test_passed = test_filters() and test_passed
print("Removed software breakpoint")
target.remove_breakpoint(addr)
test_passed = test_filters() and test_passed
test_count += 1
if test_passed:
test_pass_count += 1
print("TEST PASSED")
else:
print("TEST FAILED")
print("\nTest Summary:")
print("Pass count %i of %i tests" % (test_pass_count, test_count))
if test_pass_count == test_count:
print("CORTEX TEST PASSED")
else:
print("CORTEX TEST FAILED")
target.reset()
result.passed = test_count == test_pass_count
return result
def basic_test(board_id, file):
with ConnectHelper.session_with_chosen_probe(
unique_id=board_id, **get_session_options()) as session:
board = session.board
addr = 0
size = 0
f = None
binary_file = "l1_"
if file is None:
binary_file = get_test_binary_path(board.test_binary)
else:
binary_file = file
print("binary file: %s" % binary_file)
memory_map = board.target.get_memory_map()
ram_region = memory_map.get_default_region_of_type(MemoryType.RAM)
rom_region = memory_map.get_boot_memory()
addr = ram_region.start
size = 0x502
addr_bin = rom_region.start
target = board.target
flash = rom_region.flash
print("\n\n------ GET Unique ID ------")
print("Unique ID: %s" % board.unique_id)
print("\n\n------ TEST READ / WRITE CORE REGISTER ------")
pc = target.read_core_register('pc')
print("initial pc: 0x%X" % target.read_core_register('pc'))
# write in pc dummy value
target.write_core_register('pc', 0x3D82)
print("now pc: 0x%X" % target.read_core_register('pc'))
# write initial pc value
target.write_core_register('pc', pc)
print("initial pc value rewritten: 0x%X" %
target.read_core_register('pc'))
msp = target.read_core_register('msp')
psp = target.read_core_register('psp')
print("MSP = 0x%08x; PSP = 0x%08x" % (msp, psp))
if 'faultmask' in target.core_registers.by_name:
control = target.read_core_register('control')
faultmask = target.read_core_register('faultmask')
basepri = target.read_core_register('basepri')
primask = target.read_core_register('primask')
print(
"CONTROL = 0x%02x; FAULTMASK = 0x%02x; BASEPRI = 0x%02x; PRIMASK = 0x%02x"
% (control, faultmask, basepri, primask))
else:
control = target.read_core_register('control')
primask = target.read_core_register('primask')
print("CONTROL = 0x%02x; PRIMASK = 0x%02x" % (control, primask))
target.write_core_register('primask', 1)
newPrimask = target.read_core_register('primask')
print("New PRIMASK = 0x%02x" % newPrimask)
target.write_core_register('primask', primask)
newPrimask = target.read_core_register('primask')
print("Restored PRIMASK = 0x%02x" % newPrimask)
if target.selected_core.has_fpu:
s0 = target.read_core_register('s0')
print("S0 = %g (0x%08x)" % (s0, float32_to_u32(s0)))
target.write_core_register('s0', math.pi)
newS0 = target.read_core_register('s0')
print("New S0 = %g (0x%08x)" % (newS0, float32_to_u32(newS0)))
target.write_core_register('s0', s0)
newS0 = target.read_core_register('s0')
print("Restored S0 = %g (0x%08x)" % (newS0, float32_to_u32(newS0)))
print("\n\n------ TEST HALT / RESUME ------")
print("resume")
target.resume()
sleep(0.2)
print("halt")
target.halt()
print("HALT: pc: 0x%X" % target.read_core_register('pc'))
sleep(0.2)
print("\n\n------ TEST STEP ------")
print("reset and halt")
target.reset_and_halt()
currentPC = target.read_core_register('pc')
print("HALT: pc: 0x%X" % currentPC)
sleep(0.2)
for i in range(4):
print("step")
target.step()
newPC = target.read_core_register('pc')
print("STEP: pc: 0x%X" % newPC)
sleep(0.2)
print("\n\n------ TEST RANGE STEP ------")
# Add some extra room before end of memory, and a second copy so there are instructions
# after the final bkpt. Add 1 because region end is always odd.
test_addr = ram_region.end + 1 - len(RANGE_STEP_CODE) * 2 - 32
# Since the end address is inclusive, we need to exclude the last instruction.
test_end_addr = test_addr + len(RANGE_STEP_CODE) - 2
print("range start = %#010x; range_end = %#010x" %
(test_addr, test_end_addr))
# Load up some code into ram to test range step.
target.write_memory_block8(test_addr, RANGE_STEP_CODE * 2)
check_data = target.read_memory_block8(test_addr,
len(RANGE_STEP_CODE) * 2)
if not same(check_data, RANGE_STEP_CODE * 2):
print("Failed to write range step test code to RAM")
else:
print("wrote range test step code to RAM successfully")
target.write_core_register('pc', test_addr)
currentPC = target.read_core_register('pc')
print("start PC: 0x%X" % currentPC)
target.step(start=test_addr, end=test_end_addr)
newPC = target.read_core_register('pc')
print("end PC: 0x%X" % newPC)
# Now test again to ensure the bkpt stops it.
target.write_core_register('pc', test_addr)
currentPC = target.read_core_register('pc')
print("start PC: 0x%X" % currentPC)
target.step(start=test_addr, end=test_end_addr + 4) # include bkpt
newPC = target.read_core_register('pc')
print("end PC: 0x%X" % newPC)
halt_reason = target.get_halt_reason()
print("halt reason: %s (should be BREAKPOINT)" % halt_reason.name)
print("\n\n------ TEST READ / WRITE MEMORY ------")
target.halt()
print("READ32/WRITE32")
val = randrange(0, 0xffffffff)
print("write32 0x%X at 0x%X" % (val, addr))
target.write_memory(addr, val)
res = target.read_memory(addr)
print("read32 at 0x%X: 0x%X" % (addr, res))
if res != val:
print("ERROR in READ/WRITE 32")
print("\nREAD16/WRITE16")
val = randrange(0, 0xffff)
print("write16 0x%X at 0x%X" % (val, addr + 2))
target.write_memory(addr + 2, val, 16)
res = target.read_memory(addr + 2, 16)
print("read16 at 0x%X: 0x%X" % (addr + 2, res))
if res != val:
print("ERROR in READ/WRITE 16")
print("\nREAD8/WRITE8")
val = randrange(0, 0xff)
print("write8 0x%X at 0x%X" % (val, addr + 1))
target.write_memory(addr + 1, val, 8)
res = target.read_memory(addr + 1, 8)
print("read8 at 0x%X: 0x%X" % (addr + 1, res))
if res != val:
print("ERROR in READ/WRITE 8")
print("\n\n------ TEST READ / WRITE MEMORY BLOCK ------")
data = [randrange(1, 50) for x in range(size)]
target.write_memory_block8(addr, data)
block = target.read_memory_block8(addr, size)
error = False
for i in range(len(block)):
if (block[i] != data[i]):
error = True
print("ERROR: 0x%X, 0x%X, 0x%X!!!" %
((addr + i), block[i], data[i]))
if error:
print("TEST FAILED")
else:
print("TEST PASSED")
print("\n\n------ TEST RESET ------")
target.reset()
sleep(0.1)
target.halt()
for i in range(5):
target.step()
print("pc: 0x%X" % target.read_core_register('pc'))
print("\n\n------ TEST PROGRAM/ERASE PAGE ------")
# Fill 3 pages with 0x55
sector_size = rom_region.sector_size
page_size = rom_region.page_size
sectors_to_test = min(rom_region.length // sector_size, 3)
addr_flash = rom_region.start + rom_region.length - sector_size * sectors_to_test
fill = [0x55] * page_size
for i in range(0, sectors_to_test):
address = addr_flash + sector_size * i
# Test only supports a location with 3 aligned
# pages of the same size
current_page_size = flash.get_page_info(addr_flash).size
assert page_size == current_page_size
assert address % current_page_size == 0
print("Erasing sector @ 0x%x (%d bytes)" % (address, sector_size))
flash.init(flash.Operation.ERASE)
flash.erase_sector(address)
print("Verifying erased sector @ 0x%x (%d bytes)" %
(address, sector_size))
data = target.read_memory_block8(address, sector_size)
if data != [flash.region.erased_byte_value] * sector_size:
print("FAILED to erase sector @ 0x%x (%d bytes)" %
(address, sector_size))
else:
print("Programming page @ 0x%x (%d bytes)" %
(address, page_size))
flash.init(flash.Operation.PROGRAM)
flash.program_page(address, fill)
print("Verifying programmed page @ 0x%x (%d bytes)" %
(address, page_size))
data = target.read_memory_block8(address, page_size)
if data != fill:
print("FAILED to program page @ 0x%x (%d bytes)" %
(address, page_size))
# Erase the middle sector
if sectors_to_test > 1:
address = addr_flash + sector_size
print("Erasing sector @ 0x%x (%d bytes)" % (address, sector_size))
flash.init(flash.Operation.ERASE)
flash.erase_sector(address)
flash.cleanup()
print("Verifying erased sector @ 0x%x (%d bytes)" %
(address, sector_size))
data = target.read_memory_block8(address, sector_size)
if data != [flash.region.erased_byte_value] * sector_size:
print("FAILED to erase sector @ 0x%x (%d bytes)" %
(address, sector_size))
# Re-verify the 1st and 3rd page were not erased, and that the 2nd page is fully erased
did_pass = False
for i in range(0, sectors_to_test):
address = addr_flash + sector_size * i
print("Verifying page @ 0x%x (%d bytes)" % (address, page_size))
data = target.read_memory_block8(address, page_size)
expected = ([flash.region.erased_byte_value] *
page_size) if (i == 1) else fill
did_pass = (data == expected)
if not did_pass:
print("FAILED verify for page @ 0x%x (%d bytes)" %
(address, page_size))
break
if did_pass:
print("TEST PASSED")
else:
print("TEST FAILED")
print("\n\n----- FLASH NEW BINARY -----")
FileProgrammer(session).program(binary_file, base_address=addr_bin)
target.reset()
