def main(): pytrellis.load_database("../../../database") pytrellis.load_database("../../../database") def per_job(job): def get_substs(regtype="", regen="OFF", regset="RESET", srmode="ASYNC", regmode="FF", ceimux="1", ceomux="1", datamux="PADDO"): clkimux = "CLK" clkomux = "CLK" if regen == "ON": reg = "{}:::REGSET={},{}REGMODE={}".format(regtype, regset, "IN" if regtype == "FF" else "OUT", regmode) if regmode == "LATCH": if regtype == "FF": clkimux = "CLK:::CLK=#INV" # clk is inverted for latches else: clkomux = "CLK:::CLK=#INV" # clk is inverted for latches else: reg = "" if side in ("T, B"): s = "S" else: s = "" return dict(loc=loc, reg=reg, s=s, pin=pin, srmode=srmode, clkimux=clkimux, clkomux=clkomux, ceimux=ceimux, ceomux=ceomux, datamux=datamux) cfg = job["cfg"] loc = job["site"] iol = job["iol"] side = job["side"] pin = job["pin"] cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "iologic.ncl" nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.FF".format(iol), ["OFF", "ON"], lambda x: get_substs(regtype="FF", regen=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.FF.INREGMODE".format(iol), ["FF", "LATCH"], lambda x: get_substs(regtype="FF", regen="ON", regmode=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.FF.REGSET".format(iol), ["SET", "RESET"], lambda x: get_substs(regtype="FF", regen="ON", regset=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.OUTREG".format(iol), ["OFF", "ON"], lambda x: get_substs(regtype="OUTREG", regen=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.OUTREG.REGSET".format(iol), ["SET", "RESET"], lambda x: get_substs(regtype="OUTREG", regen="ON", regset=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.OUTREG.OUTREGMODE".format(iol), ["FF", "LATCH"], lambda x: get_substs(regtype="OUTREG", regen="ON", regmode=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.TSREG".format(iol), ["OFF", "ON"], lambda x: get_substs(regtype="TSREG", regen=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.TSREG.OUTREGMODE".format(iol), ["FF", "LATCH"], lambda x: get_substs(regtype="TSREG", regen="ON", regmode=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.TSREG.REGSET".format(iol), ["SET", "RESET"], lambda x: get_substs(regtype="TSREG", regen="ON", regset=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.SRMODE".format(iol), ["ASYNC", "LSR_OVER_CE"], lambda x: get_substs(srmode=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.CEIMUX".format(iol), ["CEMUX", "1"], lambda x: get_substs(ceimux=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.CEOMUX".format(iol), ["CEMUX", "1"], lambda x: get_substs(ceomux=x), empty_bitfile, False) nonrouting.fuzz_enum_setting(cfg, "PIO{}.DATAMUX_OREG".format(iol), ["PADDO", "IOLDO"], lambda x: get_substs(datamux=x), empty_bitfile, False) fuzzloops.parallel_foreach(jobs, per_job)
def main(): pytrellis.load_database("../../database") pytrellis.load_database("../../database") def per_job(job): def get_substs(mode="IREG_OREG", program=[]): if mode == "NONE": comment = "//" program = "" else: comment = "" program = "program " + "\n\t\t\t".join( ['"' + _ + ' "' for _ in program]) return dict(loc=loc, mode=mode, program=program, comment=comment) cfg = job["cfg"] loc = job["site"] iol = job["iol"] cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "iologic.ncl" modes = [ "NONE", "IREG_OREG", "IDDRX1_ODDRX1", "IDDRXN", "ODDRXN", "MIDDRX_MODDRX" ] tie_program = ["LSRIMUX:0", "LSROMUX:0"] nonrouting.fuzz_enum_setting( cfg, "IOLOGIC{}.MODE".format(iol), modes, lambda x: get_substs(mode=x, program=["MODE:" + x] + tie_program), empty_bitfile, False) fuzzloops.parallel_foreach(jobs, per_job)
def pos_mode(args): pytrellis.load_database("../../../database") cfg = FuzzConfig(job="FINDNETS_R{}C{}".format(args.row, args.col), family="MachXO2", device="LCMXO2-1200HC", ncl="plc2route.ncl", tiles=[]) cfg.setup() netdata = isptcl.get_wires_at_position(cfg.ncd_prf, (args.row, args.col)) netnames = [x[0] for x in netdata] arcs = isptcl.get_arcs_on_wires(cfg.ncd_prf, netnames, False, defaultdict(lambda: str("mark"))) with open( "r{}c{}_{}out.txt".format(args.row, args.col, "a_" if args.a else ""), "w") as fp: for (k, v) in arcs.items(): print("{}:".format(k), file=fp) for c in v: if isinstance(c, isptcl.AmbiguousArc): print(str(c), file=fp) else: if not args.a: print("{} --> {}".format(c[0], c[1]), file=fp) fp.flush() print("", file=fp)
def main(): pytrellis.load_database("../../../database") cfg.setup() span1_re = re.compile(r'R\d+C\d+_[VH]01[NESWTLBR]\d{4}') def nn_filter(net, netnames): """ Match nets that are: in the tile according to Tcl, global nets, or span-1 nets that are accidentally left out by Tcl""" return net in netnames or nets.machxo2.is_global(net) or span1_re.match(net) def arc_filter(arc, netnames): """ Exclude arcs whose sinks are HFSN BRANCHES (HSBX0*0{0,1}). We will deal with them specially in another fuzzer. """ return not nets.machxo2.hfsn_branch_re.match(arc[1]) def fc_filter(arc, netnames): """ Ignore connections between two general routing nets. These are edge buffers which vary based on location and must be excluded from the CIB database. """ return not (nets.general_routing_re.match(arc[0]) and nets.general_routing_re.match(arc[1])) interconnect.fuzz_interconnect(config=cfg, location=(5, 10), netname_predicate=nn_filter, arc_predicate=arc_filter, fc_predicate=fc_filter, netname_filter_union=True, enable_span1_fix=True)
def main(): pytrellis.load_database("../../../database") def per_job(job): def get_substs(mode=""): if mode != "NONE": mode = "ODDRXN:::DDRMODE={}".format(mode) else: mode = "" return dict(loc=loc, mode=mode) cfg = job["cfg"] loc = job["site"] iol = job["iol"] side = job["side"] cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "iologic.ncl" nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.ODDRXN.MODE".format(iol), ["NONE", "ODDRX2", "ODDR71"], lambda x: get_substs(mode=x), empty_bitfile, False) fuzzloops.parallel_foreach(jobs, per_job)
def main(): pytrellis.load_database("../../../database") shutil.rmtree("work", ignore_errors=True) os.mkdir("work") baseline = run_get_tiles("::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 ") # baseline = pytrellis.Bitstream.read_bit("../../../minitests/math/add.bit").deserialise_chip().tiles # modified = pytrellis.Bitstream.read_bit("../../../minitests/math/sub.bit").deserialise_chip().tiles with open("ccu2_diff.txt", "w") as f: for m in ["::A0=0,B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 "]: modified = run_get_tiles(m) tile_keys = [] for t in modified: tile_keys.append(t.key()) for k in tile_keys: diff = modified[k].cram - baseline[k].cram diff_str = [ "{}F{}B{}".format("!" if b.delta < 0 else "", b.frame, b.bit) for b in diff ] print("{0: <18}{1}".format(k, " ".join(diff_str)), file=f) f.flush()
def main(): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "lsr.ncl" def per_lsr(lsrn): slices = { "0" : "A", "1" : "B", "2" : "C", "3" : "D" } def get_substs(lsrmux="LSR", srmode="LSR_OVER_CE", lsronmux="0"): if lsrmux == "INV": lsrmux = "LSR:::LSR=#INV" return dict(s=slices[lsrn], l=lsrn, lsrmux=lsrmux, srmode=srmode, lsronmux=lsronmux) nonrouting.fuzz_enum_setting(cfg, "LSR{}.LSRMUX".format(lsrn), ["LSR", "INV"], lambda x: get_substs(lsrmux=x), empty_bitfile, True) nonrouting.fuzz_enum_setting(cfg, "LSR{}.SRMODE".format(lsrn), ["LSR_OVER_CE", "ASYNC"], lambda x: get_substs(srmode=x), empty_bitfile, True) nonrouting.fuzz_enum_setting(cfg, "LSR{}.LSRONMUX".format(lsrn), ["0", "LSRMUX"], lambda x: get_substs(lsronmux=x), empty_bitfile, True) fuzzloops.parallel_foreach(["0", "1", "2", "3"], per_lsr)
def main(): pytrellis.load_database("../../../database") config = [ (46, 1, 0), (48, 1, 0), (50, 1, 0), (54, 1, 0), (56, 1, 0), (58, 1, 0), (60, 1, 0), (62, 1, 0), ] tile = pytrellis.get_tile_bitdata( pytrellis.TileLocator("ECP5", "LFE5U-25F", "EFB1_PICB1")) wsb = pytrellis.WordSettingBits() wsb.name = "BOOTADDR" for bframe, bbit, inv in config: bg = pytrellis.BitGroup() cb = pytrellis.ConfigBit() cb.frame = bframe cb.bit = bbit cb.inv = inv bg.bits.add(cb) wsb.bits.append(bg) wsb.defval.append(False) tile.add_setting_word(wsb) tile.save()
def main(): global max_row, max_col, const_id_count pytrellis.load_database(database.get_db_root()) args = parser.parse_args() const_id_count = 1 # count ID_NONE with open(args.constids) as f: for line in f: line = line.replace("(", " ") line = line.replace(")", " ") line = line.split() if len(line) == 0: continue assert len(line) == 2 assert line[0] == "X" idx = len(constids) + 1 constids[line[1]] = idx const_id_count += 1 constids["SLICE"] = constids["FACADE_SLICE"] constids["PIO"] = constids["FACADE_IO"] chip = pytrellis.Chip(dev_names[args.device]) rg = pytrellis.make_optimized_chipdb(chip) max_row = chip.get_max_row() max_col = chip.get_max_col() process_pio_db(rg, args.device) bba = write_database(args.device, chip, rg, "le")
def main(): pytrellis.load_database("../../../database") cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "reg.ncl" def per_slice(slicen): r = 0 def get_substs(regset="RESET", sd="0", lsrmode="LSR", gsr="DISABLED"): return dict(slice=slicen, r=str(r), regset=regset, sd=sd, lsrmode=lsrmode, gsr=gsr) for r in range(2): nonrouting.fuzz_enum_setting(cfg, "SLICE{}.REG{}.REGSET".format(slicen, r), ["RESET", "SET"], lambda x: get_substs(regset=x), empty_bitfile) nonrouting.fuzz_enum_setting(cfg, "SLICE{}.REG{}.SD".format(slicen, r), ["0", "1"], lambda x: get_substs(sd=x), empty_bitfile) nonrouting.fuzz_enum_setting(cfg, "SLICE{}.REG{}.LSRMODE".format(slicen, r), ["LSR", "PRLD"], lambda x: get_substs(lsrmode=x), empty_bitfile) nonrouting.fuzz_enum_setting(cfg, "SLICE{}.GSR".format(slicen), ["DISABLED", "ENABLED"], lambda x: get_substs(gsr=x), empty_bitfile) fuzzloops.parallel_foreach(["A", "B", "C", "D"], per_slice)
def main(): pytrellis.load_database("../../../database") def per_job(job): def get_substs(net, value): if net == value: settings = "{}=#SIG".format(net, net) else: settings = "{}=#INV".format(net) return dict(loc=loc, mode=mode, settings=settings, cmodel=cellmodel) loc, mult, cfg = job cellmodel = loc.split("_")[0] mode = "MULT18X18D" if cellmodel == "MULT18" else "ALU54B" cfg.setup() empty_bitfile = cfg.build_design(cfg.ncl, {}) cfg.ncl = "dspconfig.ncl" for port in ["CLK", "CE", "RST"]: for i in range(4): sig = port + str(i) nonrouting.fuzz_enum_setting(cfg, "{}.{}MUX".format(mult, sig), [sig, "INV"], lambda x: get_substs(sig, x), empty_bitfile, False) fuzzloops.parallel_foreach(jobs, per_job)
def main(): # left_end and right_end are 1200HC-specific. However, the results # also readily apply to 2000HC devices because they also have a # CENTER_EBR_CIB tile (without qualifiers). def left_end(x): return 8 if x % 2 == 0 else 7 def right_end(x): if x == 0 or x == 4: return 18 elif x == 1 or x == 5: return 19 else: return 17 pytrellis.load_database("../../../database") for job in jobs: cfg = job["cfg"] cfg.setup() netnames = [] netnames += [job["left_net"].format(left_end(x), x) for x in range(8)] netnames += [ job["right_net"].format(right_end(x), x) for x in range(8) ] interconnect.fuzz_interconnect_with_netnames( config=cfg, netnames=netnames, netname_filter_union=False)
def main(): pytrellis.load_database("../../../database") for job in jobs: cfg = job["cfg"] cfg.setup() netnames = [job["sink_net"].format(x) for x in range(16)] interconnect.fuzz_interconnect_with_netnames(config=cfg, netnames=netnames, netname_filter_union=False)
def main(): pytrellis.load_database("../../../database") chip = pytrellis.Chip("LCMXO2-1200HC") tiletypes = set() for tile in chip.get_all_tiles(): tiletypes.add(tile.info.type) for tiletype in sorted(tiletypes): dbfixup.dbfixup("MachXO2", device, tiletype)