def test():
filelist = [codedir + 'partselect_assign.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
c_analyzer = VerilogControlflowAnalyzer(
topmodule,
terms,
binddict,
resolved_terms=optimizer.getResolvedTerms(),
resolved_binddict=optimizer.getResolvedBinddict(),
constlist=optimizer.getConstlist())
output = []
for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x: str(x)):
tree = c_analyzer.makeTree(tk)
output.append(str(tk) + ': ' + tree.tocode())
rslt = '\n'.join(output) + '\n'
print(rslt)
assert (expected == rslt)
def main():
INFO = "Verilog module signal/module dataflow analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("--nobind",
action="store_true",
dest="nobind",
default=False,
help="No binding traversal, Default=False")
optparser.add_option(
"--noreorder",
action="store_true",
dest="noreorder",
default=False,
help="No reordering of binding dataflow, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
CIRCUIT = options.topmodule
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
top = options.topmodule
fsm_vars = tuple(['state'])
## fsm_vars = tuple(['dpll_state'])
## fsm_vars = tuple(['s1','s0'])
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
print("")
name = 'test'
if CIRCUIT == "add_serial":
state_var = CDFG.newScope('add_serial', 'state')
clk = CDFG.newScope('add_serial', 'clk')
rst = CDFG.newScope('add_serial', 'rst')
elif CIRCUIT == "bbara":
state_var = CDFG.newScope('top', 'state')
clk = CDFG.newScope('top', 'clk')
rst = None
elif CIRCUIT == "dma_rrarb":
state_var = CDFG.newScope('dma_rrarb', 'state')
clk = CDFG.newScope('dma_rrarb', 'HCLK')
rst = CDFG.newScope('dma_rrarbrb', 'HRSTn')
elif CIRCUIT == "mc_timing":
state_var = CDFG.newScope('mc_timing', 'state')
clk = CDFG.newScope('mc_timing', 'clk')
rst = CDFG.newScope('mc_timing', 'rst')
elif CIRCUIT == "correlator":
state_var = CDFG.newScope('correlator', 'state')
clk = CDFG.newScope('correlator', 'clk')
rst = CDFG.newScope('correlator', 'rst_n')
fsm_obj = fsms[state_var]
if CIRCUIT == "add_serial":
state_list = [
CDFG.newScope('add_serial', 'IDLE'),
CDFG.newScope('add_serial', 'ADD'),
CDFG.newScope('add_serial', 'DONE')
]
elif CIRCUIT == "bbara":
state_list = [
CDFG.newScope('top', 'st0'),
CDFG.newScope('top', 'st1'),
CDFG.newScope('top', 'st2'),
CDFG.newScope('top', 'st3'),
CDFG.newScope('top', 'st4'),
CDFG.newScope('top', 'st5'),
CDFG.newScope('top', 'st6'),
CDFG.newScope('top', 'st7'),
CDFG.newScope('top', 'st8'),
CDFG.newScope('top', 'st9')
]
elif CIRCUIT == "dma_rrarb":
state_list = [
CDFG.newScope('dma_rrarb', 'grant0'),
CDFG.newScope('dma_rrarb', 'grant1'),
CDFG.newScope('dma_rrarb', 'grant2'),
CDFG.newScope('dma_rrarb', 'grant3'),
CDFG.newScope('dma_rrarb', 'grant4'),
CDFG.newScope('dma_rrarb', 'grant5'),
CDFG.newScope('dma_rrarb', 'grant6'),
CDFG.newScope('dma_rrarb', 'grant7'),
]
elif CIRCUIT == "mc_timing":
state_list = [
CDFG.newScope('mc_timing', 'POR'),
CDFG.newScope('mc_timing', 'IDLE'),
CDFG.newScope('mc_timing', 'IDLE_T'),
CDFG.newScope('mc_timing', 'IDLE_T2'),
CDFG.newScope('mc_timing', 'PRECHARGE'),
CDFG.newScope('mc_timing', 'PRECHARGE_W'),
CDFG.newScope('mc_timing', 'ACTIVATE'),
CDFG.newScope('mc_timing', 'ACTIVATE_W'),
CDFG.newScope('mc_timing', 'SD_RD_WR'),
CDFG.newScope('mc_timing', 'SD_RD'),
CDFG.newScope('mc_timing', 'SD_RD_W'),
CDFG.newScope('mc_timing', 'SD_RD_LOOP'),
CDFG.newScope('mc_timing', 'SD_RD_W2'),
CDFG.newScope('mc_timing', 'SD_WR'),
CDFG.newScope('mc_timing', 'SD_WR_W'),
CDFG.newScope('mc_timing', 'BT'),
CDFG.newScope('mc_timing', 'BT_W'),
CDFG.newScope('mc_timing', 'REFR'),
CDFG.newScope('mc_timing', 'LMR0'),
CDFG.newScope('mc_timing', 'LMR1'),
CDFG.newScope('mc_timing', 'LMR2'),
CDFG.newScope('mc_timing', 'INIT0'),
CDFG.newScope('mc_timing', 'INIT'),
CDFG.newScope('mc_timing', 'INIT_W'),
CDFG.newScope('mc_timing', 'INIT_REFR1'),
CDFG.newScope('mc_timing', 'INIT_REFR1_W'),
CDFG.newScope('mc_timing', 'INIT_LMR'),
CDFG.newScope('mc_timing', 'SUSP1'),
CDFG.newScope('mc_timing', 'SUSP2'),
CDFG.newScope('mc_timing', 'SUSP3'),
CDFG.newScope('mc_timing', 'SUSP4'),
CDFG.newScope('mc_timing', 'RESUME1'),
CDFG.newScope('mc_timing', 'RESUME2'),
CDFG.newScope('mc_timing', 'BG0'),
CDFG.newScope('mc_timing', 'BG1'),
CDFG.newScope('mc_timing', 'BG2'),
CDFG.newScope('mc_timing', 'ACS_RD'),
CDFG.newScope('mc_timing', 'ACS_RD1'),
CDFG.newScope('mc_timing', 'ACS_RD2A'),
CDFG.newScope('mc_timing', 'ACS_RD2'),
CDFG.newScope('mc_timing', 'ACS_RD3'),
CDFG.newScope('mc_timing', 'ACS_RD_8_1'),
CDFG.newScope('mc_timing', 'ACS_RD_8_2'),
CDFG.newScope('mc_timing', 'ACS_RD_8_3'),
CDFG.newScope('mc_timing', 'ACS_RD_8_4'),
CDFG.newScope('mc_timing', 'ACS_RD_8_5'),
CDFG.newScope('mc_timing', 'ACS_RD_8_6'),
CDFG.newScope('mc_timing', 'ACS_WR'),
CDFG.newScope('mc_timing', 'ACS_WR1'),
CDFG.newScope('mc_timing', 'ACS_WR2'),
CDFG.newScope('mc_timing', 'ACS_WR3'),
CDFG.newScope('mc_timing', 'ACS_WR4'),
CDFG.newScope('mc_timing', 'SRAM_RD'),
CDFG.newScope('mc_timing', 'SRAM_RD0'),
CDFG.newScope('mc_timing', 'SRAM_RD1'),
CDFG.newScope('mc_timing', 'SRAM_RD2'),
CDFG.newScope('mc_timing', 'SRAM_RD3'),
CDFG.newScope('mc_timing', 'SRAM_RD4'),
CDFG.newScope('mc_timing', 'SRAM_WR'),
CDFG.newScope('mc_timing', 'SRAM_WR0'),
CDFG.newScope('mc_timing', 'SCS_RD'),
CDFG.newScope('mc_timing', 'SCS_RD1'),
CDFG.newScope('mc_timing', 'SCS_RD2'),
CDFG.newScope('mc_timing', 'SCS_WR'),
CDFG.newScope('mc_timing', 'SCS_WR1'),
CDFG.newScope('mc_timing', 'SCS_ERR')
]
elif CIRCUIT == "correlator":
state_list = [
CDFG.newScope('correlator', 'WAITING'),
CDFG.newScope('correlator', 'DECIDING'),
CDFG.newScope('correlator', 'OFFSETTING'),
CDFG.newScope('correlator', 'RUNNING'),
CDFG.newScope('correlator', 'IDLE'),
CDFG.newScope('correlator', 'LOCKED'),
CDFG.newScope('correlator', 'READ_RANK'),
CDFG.newScope('correlator', 'default')
]
cdfg =\
CDFG.ControlDataFlowGraph(name, fsm_obj, state_var, clk, rst,
state_list, constlist,
resolved_terms, resolved_binddict)
cdfg.generate()
# fsm
cdfg.fsm_obj.view()
print("")
PIs = cdfg.getPIs()
# exempt clk
PIs.remove(cdfg.clk)
# and reset from scrambling
if cdfg.rst:
PIs.remove(cdfg.rst)
total_bits = 0
for PI in PIs:
total_bits += cdfg.getNumBitsOfVar(PI)
print("number of scrambled bits: " + str(total_bits / 2))
cdfg.scramblePIBits(total_bits / 2)
num_ex_states = 1
for ex_state_i in range(num_ex_states):
src = cdfg.state_list[ex_state_i]
dst = cdfg.state_list[ex_state_i + 1]
delay = CDFG.newScope(top, 'delay' + str(ex_state_i))
## delay = CDFG.newScope('add_serial', 'delay'+str(ex_state_i))
cdfg.insCopyState(src, dst, delay)
## cdfg.insDelayState(src, dst, delay)
num_bits = 6
# nonZeroStates test
(all_trans_freqs, num_PIs) = cdfg.getTransFreqs()
for row in all_trans_freqs:
print(row)
print("")
for i in range(len(cdfg.state_list)):
trans_freqs = cdfg.nonZeroStates(all_trans_freqs[i],\
cdfg.state_list[i], num_bits)
all_trans_freqs[i] = trans_freqs
## (all_trans_freqs, num_PIs) = cdfg.getTransFreqs()
for row in all_trans_freqs:
print(row)
print("")
## cdfg.toCode(options.topmodule, options.topmodule + '_codegen.v')
## cdfg.toCode('add_serial', 'add_serial_uniform.v')
## cdfg.toCode('add_serial', 'add_serial_scramb.v')
## cdfg.updateBinddict()
## cdfg.toCode('dma_rrarb', 'dma_rrarb_uniform_s0.v')
## cdfg.updateBinddict()
## cdfg.toCode('dma_rrarb', 'dma_rrarb_scramb_s0_b{}.v'
## .format(num_bits))
## cdfg.toCode('dma_rrarb', 'dma_rrarb_scramb_delay_b{}.v'.format(num_bits))
print("\n")
## print("num_edits = {}".format(num_edits))
## # original binds
## for var, bind in cdfg.binddict.items():
## print(var)
## print(bind[0].tostr())
#### print(bind[0].isCombination())
#### print(bind[0].alwaysinfo)
#### print(bind[0].parameterinfo)
## print("")
##
# binds by state
for state, binddict in cdfg.state_binddict.items():
print(state)
for var, binds in binddict.items():
print(var)
for bind in binds:
print(bind.tostr())
## print(bind.dest)
## print(type(bind.dest))
## print(bind.msb)
## print(type(bind.msb))
## print(bind.lsb)
## print(type(bind.lsb))
## print(bind.ptr)
## print(type(bind.ptr))
## print(bind.alwaysinfo)
## print(type(bind.alwaysinfo))
## print(bind.parameterinfo)
## print(type(bind.parameterinfo))
## print("")
print("")
print("")
def main():
INFO = "Control-flow analyzer for Verilog definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_controlflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("-s",
"--search",
dest="searchtarget",
action="append",
default=[],
help="Search Target Signal")
optparser.add_option("--graphformat",
dest="graphformat",
default="png",
help="Graph file format, Default=png")
optparser.add_option("--nograph",
action="store_true",
dest="nograph",
default=False,
help="Non graph generation")
optparser.add_option("--nolabel",
action="store_true",
dest="nolabel",
default=False,
help="State Machine Graph without Labels")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
fsm_vars = tuple(['fsm', 'state', 'count', 'cnt', 'step', 'mode'] +
options.searchtarget)
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame) + '.' +
options.graphformat,
nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
def main():
## CIRCUIT = "dma_rrarb"
CIRCUIT = "add_serial"
if CIRCUIT == "dma_rrarb":
src = "dma_rrarb/"
filelist = ["dma_rrarb_mod.v"]
topmodule = "dma_rrarb"
elif CIRCUIT == "add_serial":
src = "add_serial/"
filelist = ["add_serial_mod.v"]
topmodule = "add_serial"
dst = "./"
new_files = []
for file_name in os.listdir(src):
full_file_name = os.path.join(src, file_name)
if os.path.isfile(full_file_name):
shutil.copy(full_file_name, dst)
new_files.append(file_name)
noreorder = False
nobind = False
include = []
define = []
analyzer = VerilogDataflowAnalyzer(filelist, topmodule, noreorder, nobind,
include, define)
analyzer.generate()
## directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
fsm_vars = tuple(['state'])
canalyzer = VerilogControlflowAnalyzer(topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
name = topmodule
if CIRCUIT == "dma_rrarb":
state_var = CDFG.newScope('dma_rrarb', 'state')
clk = CDFG.newScope('dma_rrarb', 'HCLK')
rst = CDFG.newScope('dma_rrarb', 'HRSTn')
state_list = [
CDFG.newScope('dma_rrarb', 'grant0'),
CDFG.newScope('dma_rrarb', 'grant1'),
CDFG.newScope('dma_rrarb', 'grant2'),
CDFG.newScope('dma_rrarb', 'grant3'),
CDFG.newScope('dma_rrarb', 'grant4'),
CDFG.newScope('dma_rrarb', 'grant5'),
CDFG.newScope('dma_rrarb', 'grant6'),
CDFG.newScope('dma_rrarb', 'grant7'),
]
elif CIRCUIT == "add_serial":
state_var = CDFG.newScope('add_serial', 'state')
clk = CDFG.newScope('add_serial', 'clk')
rst = CDFG.newScope('add_serial', 'rst')
state_list = [
CDFG.newScope('add_serial', 'IDLE'),
CDFG.newScope('add_serial', 'ADD'),
CDFG.newScope('add_serial', 'DONE')
]
max_trials = 20
max_bits = 6
max_num_ex_states = 8
for num_ex_states in range(max_num_ex_states + 1):
## for num_ex_states in [3,4,5]:
print("num_ex_states = " + str(num_ex_states))
codegen_dir = "{}/codegen/nonZeroCopyState/d{}/".format(
topmodule, num_ex_states)
try:
os.makedirs(codegen_dir)
except OSError as e:
if e.errno != errno.EEXIST:
raise
f = open(codegen_dir + "edge_count_d{}.csv".format(num_ex_states), "w")
for i in range(max_bits):
num_bits = i + 1
for trial in range(max_trials):
print("generating code for num_bits = {}, trial = {}".format(
num_bits, trial + 1))
fsm_obj = copy.deepcopy(fsms[state_var])
cur_state_list = copy.deepcopy(state_list)
cur_constlist = copy.deepcopy(constlist)
cur_terms = copy.deepcopy(resolved_terms)
cur_binddict = copy.deepcopy(resolved_binddict)
cdfg =\
CDFG.ControlDataFlowGraph(name, fsm_obj, state_var, clk, rst,
cur_state_list, cur_constlist,
cur_terms, cur_binddict)
cdfg.generate()
PIs = cdfg.getPIs()
# exempt clk
PIs.remove(cdfg.clk)
# and reset from scrambling
if cdfg.rst:
PIs.remove(cdfg.rst)
total_bits = 0
for PI in PIs:
total_bits += cdfg.getNumBitsOfVar(PI)
cdfg.scramblePIBits(total_bits / 2)
for ex_state_i in range(num_ex_states):
src = cdfg.state_list[ex_state_i]
dst = cdfg.state_list[ex_state_i + 1]
delay = CDFG.newScope(topmodule, 'delay' + str(ex_state_i))
## cdfg.insDelayState(src, dst, delay)
cdfg.insCopyState(src, dst, delay)
(all_trans_freqs, num_PIs) = cdfg.getTransFreqs()
for state in cur_state_list:
src_i = cdfg.state_list.index(state)
trans_freqs = all_trans_freqs[src_i]
trans_freqs = cdfg.nonZeroStates(trans_freqs, state,
num_bits)
all_trans_freqs[src_i] = trans_freqs
cdfg.toCode(
topmodule, codegen_dir + "{}_d{}_b{}_t{}.v".format(
topmodule, num_ex_states, num_bits, trial + 1))
metric_val = cdfg.countConnects(all_trans_freqs)
f.write(str(metric_val) + ",")
f.write("\n")
f.close()
print("\n")
print("done")
for file_name in new_files:
os.remove(file_name)
