def generate(self):
ast = self.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
signal_visitor = SignalVisitor(moduleinfotable, self.topmodule)
signal_visitor.start_visit()
frametable = signal_visitor.getFrameTable()
if self.nobind:
self.frametable = frametable
return
bind_visitor = BindVisitor(moduleinfotable, self.topmodule, frametable,
noreorder=self.noreorder)
bind_visitor.start_visit()
dataflow = bind_visitor.getDataflows()
self.frametable = bind_visitor.getFrameTable()
self.terms = dataflow.getTerms()
self.binddict = dataflow.getBinddict()
def generate(self):
ast = self.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
signal_visitor = SignalVisitor(moduleinfotable, self.topmodule)
signal_visitor.start_visit()
frametable = signal_visitor.getFrameTable()
if self.nobind:
self.frametable = frametable
return
bind_visitor = BindVisitor(moduleinfotable, self.topmodule, frametable,
noreorder=self.noreorder)
bind_visitor.start_visit()
dataflow = bind_visitor.getDataflows()
self.frametable = bind_visitor.getFrameTable()
self.terms = dataflow.getTerms()
self.binddict = dataflow.getBinddict()
def to_module_dict(*filelist, **opt):
ast = to_ast(*filelist, **opt)
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
module_names = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
moduleinfo = moduleinfotable.getDefinitions()
module_dict = collections.OrderedDict([ (n, d.definition) for n, d in moduleinfo.items() ])
return module_dict
def to_module_dict(*filelist, **opt):
ast = to_ast(*filelist, **opt)
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
module_names = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
moduleinfo = moduleinfotable.getDefinitions()
module_dict = collections.OrderedDict([(n, d.definition)
for n, d in moduleinfo.items()])
return module_dict
def generate(self):
preprocess_define = []
if self.single_clock:
preprocess_define.append('CORAM_SINGLE_CLOCK')
if self.define:
preprocess_define.extend(self.define)
code_parser = VerilogCodeParser(self.filelist,
preprocess_include=self.include,
preprocess_define=preprocess_define)
ast = code_parser.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
instanceconvert_visitor = InstanceConvertVisitor(
moduleinfotable, self.topmodule)
instanceconvert_visitor.start_visit()
replaced_instance = instanceconvert_visitor.getMergedReplacedInstance()
replaced_instports = instanceconvert_visitor.getReplacedInstPorts()
replaced_items = instanceconvert_visitor.getReplacedItems()
new_moduleinfotable = instanceconvert_visitor.get_new_moduleinfotable()
instancereplace_visitor = InstanceReplaceVisitor(
replaced_instance, replaced_instports, replaced_items,
new_moduleinfotable)
ret = instancereplace_visitor.getAST()
# gather user-defined io-ports on top-module and parameters to connect external
frametable = instanceconvert_visitor.getFrameTable()
top_ioports = []
for i in moduleinfotable.getIOPorts(self.topmodule):
if signaltype.isClock(i) or signaltype.isReset(i): continue
top_ioports.append(i)
top_scope = ScopeChain([ScopeLabel(self.topmodule, 'module')])
top_sigs = frametable.getSignals(top_scope)
top_params = frametable.getConsts(top_scope)
for sk, sv in top_sigs.items():
if len(sk) > 2: continue
signame = sk[1].scopename
for svv in sv:
if (signame in top_ioports
and not (signaltype.isClock(signame)
or signaltype.isReset(signame))
and isinstance(svv, vast.Input)
or isinstance(svv, vast.Output)
or isinstance(svv, vast.Inout)):
port = svv
msb_val = instanceconvert_visitor.optimize(
instanceconvert_visitor.getTree(
port.width.msb, top_scope))
lsb_val = instanceconvert_visitor.optimize(
instanceconvert_visitor.getTree(
port.width.lsb, top_scope))
width = int(msb_val.value) - int(lsb_val.value) + 1
self.top_ioports[signame] = (port, width)
break
for ck, cv in top_params.items():
if len(ck) > 2: continue
signame = ck[1].scopename
param = cv[0]
if isinstance(param, vast.Genvar): continue
self.top_parameters[signame] = param
self.coram_object = instanceconvert_visitor.getCoramObject()
return ret
def generate(self):
code_parser = VerilogCodeParser(self.filelist,
preprocess_include=self.include,
preprocess_define=self.define)
ast = code_parser.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
template_parser = VerilogCodeParser( (self.template_file,) )
template_ast = template_parser.parse()
template_visitor = ModuleVisitor()
template_visitor.visit(template_ast)
templateinfotable = template_visitor.get_moduleinfotable()
instanceconvert_visitor = InstanceConvertVisitor(moduleinfotable, self.topmodule, templateinfotable)
instanceconvert_visitor.start_visit()
replaced_instance = instanceconvert_visitor.getMergedReplacedInstance()
replaced_instports = instanceconvert_visitor.getReplacedInstPorts()
replaced_items = instanceconvert_visitor.getReplacedItems()
new_moduleinfotable = instanceconvert_visitor.get_new_moduleinfotable()
instancereplace_visitor = InstanceReplaceVisitor(replaced_instance,
replaced_instports,
replaced_items,
new_moduleinfotable)
ret = instancereplace_visitor.getAST()
# gather user-defined io-ports on top-module and parameters to connect external
frametable = instanceconvert_visitor.getFrameTable()
top_ioports = []
for i in moduleinfotable.getIOPorts(self.topmodule):
if signaltype.isClock(i) or signaltype.isReset(i): continue
top_ioports.append(i)
top_sigs = frametable.getSignals( ScopeChain( [ScopeLabel(self.topmodule, 'module')] ) )
top_params = frametable.getConsts( ScopeChain( [ScopeLabel(self.topmodule, 'module')] ) )
for sk, sv in top_sigs.items():
if len(sk) > 2: continue
signame = sk[1].scopename
for svv in sv:
if (signame in top_ioports and
not (signaltype.isClock(signame) or signaltype.isReset(signame)) and
isinstance(svv, vast.Input) or isinstance(svv, vast.Output) or isinstance(svv, vast.Inout)):
port = svv
self.top_ioports[signame] = port
break
for ck, cv in top_params.items():
if len(ck) > 2: continue
signame = ck[1].scopename
param = cv[0]
if isinstance(param, vast.Genvar): continue
self.top_parameters[signame] = param
self.target_object = instanceconvert_visitor.getTargetObject()
return ret
def generate(self):
preprocess_define = []
if self.single_clock:
preprocess_define.append('CORAM_SINGLE_CLOCK')
if self.define:
preprocess_define.extend(self.define)
code_parser = VerilogCodeParser(self.filelist,
preprocess_include=self.include,
preprocess_define=preprocess_define)
ast = code_parser.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
instanceconvert_visitor = InstanceConvertVisitor(moduleinfotable, self.topmodule)
instanceconvert_visitor.start_visit()
replaced_instance = instanceconvert_visitor.getMergedReplacedInstance()
replaced_instports = instanceconvert_visitor.getReplacedInstPorts()
replaced_items = instanceconvert_visitor.getReplacedItems()
new_moduleinfotable = instanceconvert_visitor.get_new_moduleinfotable()
instancereplace_visitor = InstanceReplaceVisitor(replaced_instance,
replaced_instports,
replaced_items,
new_moduleinfotable)
ret = instancereplace_visitor.getAST()
# gather user-defined io-ports on top-module and parameters to connect external
frametable = instanceconvert_visitor.getFrameTable()
top_ioports = []
for i in moduleinfotable.getIOPorts(self.topmodule):
if signaltype.isClock(i) or signaltype.isReset(i): continue
top_ioports.append(i)
top_scope = ScopeChain( [ScopeLabel(self.topmodule, 'module')] )
top_sigs = frametable.getSignals(top_scope)
top_params = frametable.getConsts(top_scope)
for sk, sv in top_sigs.items():
if len(sk) > 2: continue
signame = sk[1].scopename
for svv in sv:
if (signame in top_ioports and
not (signaltype.isClock(signame) or signaltype.isReset(signame)) and
isinstance(svv, vast.Input) or isinstance(svv, vast.Output) or isinstance(svv, vast.Inout)):
port = svv
msb_val = instanceconvert_visitor.optimize(instanceconvert_visitor.getTree(port.width.msb, top_scope))
lsb_val = instanceconvert_visitor.optimize(instanceconvert_visitor.getTree(port.width.lsb, top_scope))
width = int(msb_val.value) - int(lsb_val.value) + 1
self.top_ioports[signame] = (port, width)
break
for ck, cv in top_params.items():
if len(ck) > 2: continue
signame = ck[1].scopename
param = cv[0]
if isinstance(param, vast.Genvar): continue
self.top_parameters[signame] = param
self.coram_object = instanceconvert_visitor.getCoramObject()
return ret
def generate(self):
code_parser = VerilogCodeParser(self.filelist,
preprocess_include=self.include,
preprocess_define=self.define)
ast = code_parser.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
template_parser = VerilogCodeParser((self.template_file, ))
template_ast = template_parser.parse()
template_visitor = ModuleVisitor()
template_visitor.visit(template_ast)
templateinfotable = template_visitor.get_moduleinfotable()
instanceconvert_visitor = InstanceConvertVisitor(
moduleinfotable, self.topmodule, templateinfotable)
instanceconvert_visitor.start_visit()
replaced_instance = instanceconvert_visitor.getMergedReplacedInstance()
replaced_instports = instanceconvert_visitor.getReplacedInstPorts()
replaced_items = instanceconvert_visitor.getReplacedItems()
new_moduleinfotable = instanceconvert_visitor.get_new_moduleinfotable()
instancereplace_visitor = InstanceReplaceVisitor(
replaced_instance, replaced_instports, replaced_items,
new_moduleinfotable)
ret = instancereplace_visitor.getAST()
# gather user-defined io-ports on top-module and parameters to connect external
frametable = instanceconvert_visitor.getFrameTable()
top_ioports = []
for i in moduleinfotable.getIOPorts(self.topmodule):
if signaltype.isClock(i) or signaltype.isReset(i): continue
top_ioports.append(i)
top_sigs = frametable.getSignals(
ScopeChain([ScopeLabel(self.topmodule, 'module')]))
top_params = frametable.getConsts(
ScopeChain([ScopeLabel(self.topmodule, 'module')]))
for sk, sv in top_sigs.items():
if len(sk) > 2: continue
signame = sk[1].scopename
for svv in sv:
if (signame in top_ioports
and not (signaltype.isClock(signame)
or signaltype.isReset(signame))
and isinstance(svv, vast.Input)
or isinstance(svv, vast.Output)
or isinstance(svv, vast.Inout)):
port = svv
self.top_ioports[signame] = port
break
for ck, cv in top_params.items():
if len(ck) > 2: continue
signame = ck[1].scopename
param = cv[0]
if isinstance(param, vast.Genvar): continue
self.top_parameters[signame] = param
self.target_object = instanceconvert_visitor.getTargetObject()
return ret
def generateTestbench():
optionParser = OptionParser()
optionParser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optionParser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optionParser.add_option("-T",
dest="targetModuleName",
default=None,
help="Predicted module name")
(options, args) = optionParser.parse_args()
fileList = args
for f in fileList:
if not os.path.exists(f):
errPrintAndExit("File :" + f + " does not exist.")
ast = None
try:
ast, directives = parse(fileList,
preprocess_include=options.include,
preprocess_define=options.define)
except Exception as e:
errPrintAndExit('Syntax error: (Line is probably not correct)\n' +
str(e))
if not ast:
errPrintAndExit("No module found.")
modVisitor = ModuleVisitor()
modVisitor.visit(ast)
modules = modVisitor.get_modulenames()
if len(modules) == 0:
errPrintAndExit("No module found.")
pos = 0
moduleNotFound = False
if options.targetModuleName and len(modules) > 1:
moduleNotFound = True
if options.targetModuleName in modules:
pos = modules.index(options.targetModuleName)
moduleNotFound = False
infoTable = modVisitor.get_moduleinfotable()
codeGen = ASTCodeGenerator()
ret = modules[pos] + " "
params = infoTable.getParamNames(modules[pos])
print('`include "timescale.v"\n\n')
print("`define CLK_EDGE_WIDTH 5\n")
print("\nmodule " + modules[pos] + "_test();\n")
for p in params:
print("localparam " + p + " = " + UNKNOWN + ";")
print(
"\n\nreg clk;\nreg rst;\n") # TODO: auto find clock and rst of module
if params:
ret += "#("
for p in params:
ret += "." + p + "(" + p + "), "
ret = ret[:-2] + ") " # removing the last ', '
ret += "tb_" + modules[pos] + "("
ret = formatLine(ret, maxLineLen=100)
moduleSignals = infoTable.getSignals(modules[pos])
first = True
curLine = 0
regs = ["clk", "rst"]
# alignment = spacesForAlignment(ret, first=False, maxLen=20)
alignment = " " * 4
while moduleSignals:
signal = moduleSignals.popitem(
last=False)[1][0] # this is how you access the signal
ioType = type(signal).__name__ # Input, Output, Inout
width = None
if signal.width:
width = codeGen.visit(signal.width) # we generate only once
if ioType == "Input":
s = "reg "
regs.append(signal.name + "_tb")
elif ioType == "Inout":
s = "wire " # TODO: add support for three state - wire and reg and assigments
else: # Wire
s = "wire "
if width:
s += width + " "
print(s + signal.name + "_tb;")
if first:
curLine = signal.lineno - 1
first = False
while curLine < signal.lineno:
print("")
ret += "\n"
curLine += 1
ret += alignment + "." + signal.name + "(" + signal.name + "_tb),"
if not first:
# remove last ','
ret = ret[:-1] + "\n" + alignment
ret += ");"
alignment = " "
print("\n\ninitial begin")
print('$dumpfile("signals.vcd");')
print('$dumpvars;')
for r in regs:
print(alignment + r + " = " + INITIAL + ";")
print("end\n")
print("always #`CLK_EDGE_WIDTH clk = ~clk;\n")
print(ret)
print("\n\nendmodule")
if moduleNotFound:
errPrint("First module selected.")
def copyModule():
optionParser = OptionParser()
optionParser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optionParser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optionParser.add_option("-T",
dest="targetModuleName",
default=None,
help="Predicted module name")
(options, args) = optionParser.parse_args()
fileList = args
for f in fileList:
if not os.path.exists(f):
errPrintAndExit("File :" + f + " does not exist.")
ast = None
try:
ast, directives = parse(fileList,
preprocess_include=options.include,
preprocess_define=options.define)
except Exception as e:
errPrintAndExit('Syntax error: (Line is probably not correct)\n' +
str(e))
if not ast:
errPrintAndExit("No module found.")
modVisitor = ModuleVisitor()
modVisitor.visit(ast)
modules = modVisitor.get_modulenames()
if len(modules) == 0:
errPrintAndExit("No module found.")
pos = 0
moduleNotFound = False
if options.targetModuleName and len(modules) > 1:
moduleNotFound = True
if options.targetModuleName in modules:
pos = modules.index(options.targetModuleName)
moduleNotFound = False
infoTable = modVisitor.get_moduleinfotable()
# print(infoTable.getIOPorts(modules[pos])) returns only ports without line numbers and width
ret = modules[pos] + " "
params = infoTable.getParamNames(modules[pos])
if params:
ret += "#("
for p in params:
ret += "." + p + "(value), "
ret = ret[:-2] + ") " # removing the last ', '
ret += "u_" + modules[pos] + "("
ret = formatLine(ret, maxLineLen=100)
moduleSignals = infoTable.getSignals(modules[pos])
first = True
curLine = 0
# alignment = spacesForAlignment(ret, first=False, maxLen=20)
alignment = " " * 4
while moduleSignals:
signal = moduleSignals.popitem(
last=False)[1][0] # this is how you access the signal
if first:
curLine = signal.lineno - 1
first = False
while curLine < signal.lineno:
ret += "\n"
curLine += 1
ret += alignment + "." + signal.name + "(),"
if not first:
# remove last ','
ret = ret[:-1] + "\n" + alignment
ret += ");"
print(ret)
if moduleNotFound:
errPrint("First module selected.")