def __init__(self, filelist, topmodule='TOP', noreorder=False, nobind=False):
self.topmodule = topmodule
self.terms = {}
self.binddict = {}
self.frametable = None
VerilogCodeParser.__init__(self, filelist)
self.noreorder = noreorder
self.nobind = nobind
def __init__(self, filelist, topmodule='TOP', noreorder=False, nobind=False,
preprocess_include=None,
preprocess_define=None):
self.topmodule = topmodule
self.terms = {}
self.binddict = {}
self.frametable = None
VerilogCodeParser.__init__(self, filelist,
preprocess_include=preprocess_include,
preprocess_define=preprocess_define)
self.noreorder = noreorder
self.nobind = nobind
def main():
INFO = "Code converter from AST"
VERSION = pyverilog.__version__
USAGE = "Usage: python example_codegen.py file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f):
raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
codeparser = VerilogCodeParser(filelist,
preprocess_include=options.include,
preprocess_define=options.define)
ast = codeparser.parse()
directives = codeparser.get_directives()
codegen = ASTCodeGenerator()
rslt = codegen.visit(ast)
print(rslt)
def __init__(self, filelist, topmodule='TOP', noreorder=False, nobind=False,
preprocess_include=None,
preprocess_define=None):
self.topmodule = topmodule
self.terms = {}
self.binddict = {}
self.frametable = None
files = filelist if isinstance(filelist, tuple) or isinstance(filelist, list) else [ filelist ]
VerilogCodeParser.__init__(self, files,
preprocess_include=preprocess_include,
preprocess_define=preprocess_define)
self.noreorder = noreorder
self.nobind = nobind
def to_ast(*filelist, **opt):
include = opt['include'] if 'include' in opt else ()
define = opt['define'] if 'define' in opt else ()
if not isinstance(include, tuple) and not isinstance(include, list):
raise TypeError('"include" option of read_verilog must be tuple or list, not %s' %
type(include))
if not isinstance(include, tuple) and not isinstance(include, list):
raise TypeError('"include" option of read_verilog must be tuple or list, not %s' %
type(include))
code_parser = VerilogCodeParser(filelist,
preprocess_include=include,
preprocess_define=define)
ast = code_parser.parse()
return ast
def to_ast(*filelist, **opt):
include = opt['include'] if 'include' in opt else ()
define = opt['define'] if 'define' in opt else ()
if not isinstance(include, tuple) and not isinstance(include, list):
raise TypeError('"include" option of read_verilog must be tuple or list, not %s' %
type(include))
if not isinstance(include, tuple) and not isinstance(include, list):
raise TypeError('"include" option of read_verilog must be tuple or list, not %s' %
type(include))
code_parser = VerilogCodeParser(filelist,
preprocess_include=include,
preprocess_define=define)
ast = code_parser.parse()
return ast
def main():
INFO = "Verilog ast modificator parser"
VERSION = version.VERSION
USAGE = "Usage: python parser.py file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option(
"-v", "--version", action="store_true", dest="showversion", default=False, help="Show the version"
)
optparser.add_option("-o", "--output", dest="outputfile", default="out.v", help="Output File name, Default=out.v")
optparser.add_option("-I", "--include", dest="include", action="append", default=[], help="Include path")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f):
raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
codeparser = VerilogCodeParser(filelist, preprocess_include=options.include)
ast = codeparser.parse()
directives = codeparser.get_directives()
inserter = DriveInserter("DRIVE")
rslt = inserter.generate(ast)
asttocode = ASTCodeGenerator()
code = asttocode.visit(rslt)
f = open(options.outputfile, "w")
f.write(code)
f.close()
def main():
INFO = "Verilog ast modificator parser"
VERSION = version.VERSION
USAGE = "Usage: python parser.py file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-o","--output",dest="outputfile",
default="out.v",help="Output File name, Default=out.v")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
codeparser = VerilogCodeParser(filelist, preprocess_include=options.include)
ast = codeparser.parse()
directives = codeparser.get_directives()
inserter = DriveInserter('DRIVE')
rslt = inserter.generate(ast)
asttocode = ASTCodeGenerator()
code = asttocode.visit(rslt)
f = open(options.outputfile, 'w')
f.write(code)
f.close()
def top_gen_main():
auto_mode_params = {}
core_inst = ""
top_gen_conf_path = "/home/murai/openrisc/orpsoc-cores-ng/systems/atlys/top_generating/atlys_topgen" #TODO: input("Give the output folder for the top generation!\n")
top_gen_output_path = top_gen_conf_path.split("/")[:-1]
is_interactive = input("Interactive (I) or automatic(A) mode?\n")
if is_interactive == "I":
top_modul_file_name = input("Give the top module's filename (with extension): \n")
else:
auto_mode_param_file_path = topgen.automatic_mode_functions.create_auto_mode_param_file(top_gen_output_path)
auto_mode_params = topgen.automatic_mode_functions.handle_conf_file(auto_mode_param_file_path)
top_modul_file_name = auto_mode_params["Top module's filename"]
top_modul_file_name = str(top_modul_file_name).replace(" ", "")
top_modul_file_name = str(top_modul_file_name).replace("\n", "")
# Open configuration file
topgen.handleConfFile.processConfFile(top_gen_conf_path)
# Set the environment and look for source files
sourcePreparations = SourcePreparations(topgen.handleConfFile.module_name, top_gen_output_path, is_interactive)
# Instantiation from the source list
for source in range(len(sourcePreparations.source_list)):
codeParser = VerilogCodeParser(filelist=[sourcePreparations.source_list[source]])
sAst = codeParser.parse()
moduleNode = findTopGen(sAst, top_gen_output_path)
core_inst += moduleNode.instantiate(topgen.handleConfFile.instantiation_name[source], topgen.handleConfFile.rank[source])
# Set the comment if any
output = set_comment_field(is_interactive, auto_mode_params)
# Set the top module's includes if any
top_modul_include_list = set_includes(is_interactive, auto_mode_params)
for element in top_modul_include_list:
output += element
# Set the top module's parameters if any
top_modul_param_list = set_top_modul_params(is_interactive, auto_mode_params)
for param in top_modul_param_list:
output += param
# Create the top.v file
output += core_inst
writeToFile(output, top_gen_output_path, top_modul_file_name)
def main():
INFO = "Code converter from AST"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_codegen.py file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
codeparser = VerilogCodeParser(filelist,
preprocess_include=options.include,
preprocess_define=options.define)
ast = codeparser.parse()
directives = codeparser.get_directives()
codegen = ASTCodeGenerator()
rslt = codegen.visit(ast)
print(rslt)
def test():
filelist = [codedir + 'instance_array.v']
output = 'preprocess.out'
include = None
define = None
parser = VerilogCodeParser(filelist,
preprocess_include=include,
preprocess_define=define)
ast = parser.parse()
directives = parser.get_directives()
output = StringIO()
ast.show(buf=output)
for lineno, directive in directives:
output.write('Line %d : %s' % (lineno, directive))
rslt = output.getvalue()
print(rslt)
assert (expected == rslt)
def test():
filelist = [codedir + 'instance_array.v']
output = 'preprocess.out'
include = None
define = None
parser = VerilogCodeParser(filelist,
preprocess_include=include,
preprocess_define=define)
ast = parser.parse()
directives = parser.get_directives()
output = StringIO()
ast.show(buf=output)
for lineno, directive in directives:
output.write('Line %d : %s' % (lineno, directive))
rslt = output.getvalue()
print(rslt)
assert(expected == rslt)
def generate(self):
preprocess_define = []
if self.single_clock:
preprocess_define.append('CORAM_SINGLE_CLOCK')
if self.define:
preprocess_define.extend(self.define)
code_parser = VerilogCodeParser(self.filelist,
preprocess_include=self.include,
preprocess_define=preprocess_define)
ast = code_parser.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
instanceconvert_visitor = InstanceConvertVisitor(moduleinfotable, self.topmodule)
instanceconvert_visitor.start_visit()
replaced_instance = instanceconvert_visitor.getMergedReplacedInstance()
replaced_instports = instanceconvert_visitor.getReplacedInstPorts()
replaced_items = instanceconvert_visitor.getReplacedItems()
new_moduleinfotable = instanceconvert_visitor.get_new_moduleinfotable()
instancereplace_visitor = InstanceReplaceVisitor(replaced_instance,
replaced_instports,
replaced_items,
new_moduleinfotable)
ret = instancereplace_visitor.getAST()
# gather user-defined io-ports on top-module and parameters to connect external
frametable = instanceconvert_visitor.getFrameTable()
top_ioports = []
for i in moduleinfotable.getIOPorts(self.topmodule):
if signaltype.isClock(i) or signaltype.isReset(i): continue
top_ioports.append(i)
top_scope = ScopeChain( [ScopeLabel(self.topmodule, 'module')] )
top_sigs = frametable.getSignals(top_scope)
top_params = frametable.getConsts(top_scope)
for sk, sv in top_sigs.items():
if len(sk) > 2: continue
signame = sk[1].scopename
for svv in sv:
if (signame in top_ioports and
not (signaltype.isClock(signame) or signaltype.isReset(signame)) and
isinstance(svv, vast.Input) or isinstance(svv, vast.Output) or isinstance(svv, vast.Inout)):
port = svv
msb_val = instanceconvert_visitor.optimize(instanceconvert_visitor.getTree(port.width.msb, top_scope))
lsb_val = instanceconvert_visitor.optimize(instanceconvert_visitor.getTree(port.width.lsb, top_scope))
width = int(msb_val.value) - int(lsb_val.value) + 1
self.top_ioports[signame] = (port, width)
break
for ck, cv in top_params.items():
if len(ck) > 2: continue
signame = ck[1].scopename
param = cv[0]
if isinstance(param, vast.Genvar): continue
self.top_parameters[signame] = param
self.coram_object = instanceconvert_visitor.getCoramObject()
return ret
optparser.add_option("-o","--output",dest="outputfile",
default="out.v",help="Output File name, Default=out.v")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
codeparser = VerilogCodeParser(filelist, preprocess_include=options.include)
ast = codeparser.parse()
directives = codeparser.get_directives()
inserter = DriveInserter('DRIVE')
rslt = inserter.generate(ast)
asttocode = ASTCodeGenerator()
code = asttocode.visit(rslt)
f = open(options.outputfile, 'w')
f.write(code)
f.close()
def generate(self):
code_parser = VerilogCodeParser(self.filelist,
preprocess_include=self.include,
preprocess_define=self.define)
ast = code_parser.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
template_parser = VerilogCodeParser( (self.template_file,) )
template_ast = template_parser.parse()
template_visitor = ModuleVisitor()
template_visitor.visit(template_ast)
templateinfotable = template_visitor.get_moduleinfotable()
instanceconvert_visitor = InstanceConvertVisitor(moduleinfotable, self.topmodule, templateinfotable)
instanceconvert_visitor.start_visit()
replaced_instance = instanceconvert_visitor.getMergedReplacedInstance()
replaced_instports = instanceconvert_visitor.getReplacedInstPorts()
replaced_items = instanceconvert_visitor.getReplacedItems()
new_moduleinfotable = instanceconvert_visitor.get_new_moduleinfotable()
instancereplace_visitor = InstanceReplaceVisitor(replaced_instance,
replaced_instports,
replaced_items,
new_moduleinfotable)
ret = instancereplace_visitor.getAST()
# gather user-defined io-ports on top-module and parameters to connect external
frametable = instanceconvert_visitor.getFrameTable()
top_ioports = []
for i in moduleinfotable.getIOPorts(self.topmodule):
if signaltype.isClock(i) or signaltype.isReset(i): continue
top_ioports.append(i)
top_sigs = frametable.getSignals( ScopeChain( [ScopeLabel(self.topmodule, 'module')] ) )
top_params = frametable.getConsts( ScopeChain( [ScopeLabel(self.topmodule, 'module')] ) )
for sk, sv in top_sigs.items():
if len(sk) > 2: continue
signame = sk[1].scopename
for svv in sv:
if (signame in top_ioports and
not (signaltype.isClock(signame) or signaltype.isReset(signame)) and
isinstance(svv, vast.Input) or isinstance(svv, vast.Output) or isinstance(svv, vast.Inout)):
port = svv
self.top_ioports[signame] = port
break
for ck, cv in top_params.items():
if len(ck) > 2: continue
signame = ck[1].scopename
param = cv[0]
if isinstance(param, vast.Genvar): continue
self.top_parameters[signame] = param
self.target_object = instanceconvert_visitor.getTargetObject()
return ret
def generate(self):
preprocess_define = []
if self.single_clock:
preprocess_define.append('CORAM_SINGLE_CLOCK')
if self.define:
preprocess_define.extend(self.define)
code_parser = VerilogCodeParser(self.filelist,
preprocess_include=self.include,
preprocess_define=preprocess_define)
ast = code_parser.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
instanceconvert_visitor = InstanceConvertVisitor(
moduleinfotable, self.topmodule)
instanceconvert_visitor.start_visit()
replaced_instance = instanceconvert_visitor.getMergedReplacedInstance()
replaced_instports = instanceconvert_visitor.getReplacedInstPorts()
replaced_items = instanceconvert_visitor.getReplacedItems()
new_moduleinfotable = instanceconvert_visitor.get_new_moduleinfotable()
instancereplace_visitor = InstanceReplaceVisitor(
replaced_instance, replaced_instports, replaced_items,
new_moduleinfotable)
ret = instancereplace_visitor.getAST()
# gather user-defined io-ports on top-module and parameters to connect external
frametable = instanceconvert_visitor.getFrameTable()
top_ioports = []
for i in moduleinfotable.getIOPorts(self.topmodule):
if signaltype.isClock(i) or signaltype.isReset(i): continue
top_ioports.append(i)
top_scope = ScopeChain([ScopeLabel(self.topmodule, 'module')])
top_sigs = frametable.getSignals(top_scope)
top_params = frametable.getConsts(top_scope)
for sk, sv in top_sigs.items():
if len(sk) > 2: continue
signame = sk[1].scopename
for svv in sv:
if (signame in top_ioports
and not (signaltype.isClock(signame)
or signaltype.isReset(signame))
and isinstance(svv, vast.Input)
or isinstance(svv, vast.Output)
or isinstance(svv, vast.Inout)):
port = svv
msb_val = instanceconvert_visitor.optimize(
instanceconvert_visitor.getTree(
port.width.msb, top_scope))
lsb_val = instanceconvert_visitor.optimize(
instanceconvert_visitor.getTree(
port.width.lsb, top_scope))
width = int(msb_val.value) - int(lsb_val.value) + 1
self.top_ioports[signame] = (port, width)
break
for ck, cv in top_params.items():
if len(ck) > 2: continue
signame = ck[1].scopename
param = cv[0]
if isinstance(param, vast.Genvar): continue
self.top_parameters[signame] = param
self.coram_object = instanceconvert_visitor.getCoramObject()
return ret
def generate(self):
code_parser = VerilogCodeParser(self.filelist,
preprocess_include=self.include,
preprocess_define=self.define)
ast = code_parser.parse()
module_visitor = ModuleVisitor()
module_visitor.visit(ast)
modulenames = module_visitor.get_modulenames()
moduleinfotable = module_visitor.get_moduleinfotable()
template_parser = VerilogCodeParser((self.template_file, ))
template_ast = template_parser.parse()
template_visitor = ModuleVisitor()
template_visitor.visit(template_ast)
templateinfotable = template_visitor.get_moduleinfotable()
instanceconvert_visitor = InstanceConvertVisitor(
moduleinfotable, self.topmodule, templateinfotable)
instanceconvert_visitor.start_visit()
replaced_instance = instanceconvert_visitor.getMergedReplacedInstance()
replaced_instports = instanceconvert_visitor.getReplacedInstPorts()
replaced_items = instanceconvert_visitor.getReplacedItems()
new_moduleinfotable = instanceconvert_visitor.get_new_moduleinfotable()
instancereplace_visitor = InstanceReplaceVisitor(
replaced_instance, replaced_instports, replaced_items,
new_moduleinfotable)
ret = instancereplace_visitor.getAST()
# gather user-defined io-ports on top-module and parameters to connect external
frametable = instanceconvert_visitor.getFrameTable()
top_ioports = []
for i in moduleinfotable.getIOPorts(self.topmodule):
if signaltype.isClock(i) or signaltype.isReset(i): continue
top_ioports.append(i)
top_sigs = frametable.getSignals(
ScopeChain([ScopeLabel(self.topmodule, 'module')]))
top_params = frametable.getConsts(
ScopeChain([ScopeLabel(self.topmodule, 'module')]))
for sk, sv in top_sigs.items():
if len(sk) > 2: continue
signame = sk[1].scopename
for svv in sv:
if (signame in top_ioports
and not (signaltype.isClock(signame)
or signaltype.isReset(signame))
and isinstance(svv, vast.Input)
or isinstance(svv, vast.Output)
or isinstance(svv, vast.Inout)):
port = svv
self.top_ioports[signame] = port
break
for ck, cv in top_params.items():
if len(ck) > 2: continue
signame = ck[1].scopename
param = cv[0]
if isinstance(param, vast.Genvar): continue
self.top_parameters[signame] = param
self.target_object = instanceconvert_visitor.getTargetObject()
return ret