def test_active_transpiler_settings(self): """Test setting settings of active builder's transpiler.""" with pulse.build(self.backend): self.assertFalse(pulse.active_transpiler_settings()) with pulse.transpiler_settings(test_setting=1): self.assertEqual( pulse.active_transpiler_settings()['test_setting'], 1)
def test_transpiler_settings(self): """Test the transpiler settings context. Tests that two cx gates are optimized away with higher optimization level. """ twice_cx_qc = circuit.QuantumCircuit(2) twice_cx_qc.cx(0, 1) twice_cx_qc.cx(0, 1) with pulse.build(self.backend) as schedule: with pulse.transpiler_settings(optimization_level=0): builder.call_circuit(twice_cx_qc) self.assertNotEqual(len(schedule.instructions), 0) with pulse.build(self.backend) as schedule: with pulse.transpiler_settings(optimization_level=3): builder.call_circuit(twice_cx_qc) self.assertEqual(len(schedule.instructions), 0)
def test_u1(self): """Test u1 gate.""" with pulse.build(self.backend) as schedule: with pulse.transpiler_settings(layout_method="trivial"): pulse.u1(np.pi / 2, 0) reference_qc = circuit.QuantumCircuit(1) reference_qc.append(circuit.library.U1Gate(np.pi / 2), [0]) reference = compiler.schedule(reference_qc, self.backend) self.assertScheduleEqual(schedule, reference)
def test_scheduler_settings(self): """Test the circuit scheduler settings context.""" inst_map = pulse.InstructionScheduleMap() d0 = pulse.DriveChannel(0) test_x_sched = pulse.Schedule() test_x_sched += instructions.Delay(10, d0) inst_map.add('x', (0,), test_x_sched) x_qc = circuit.QuantumCircuit(2) x_qc.x(0) with pulse.build(backend=self.backend) as schedule: with pulse.transpiler_settings(basis_gates=['x']): with pulse.circuit_scheduler_settings(inst_map=inst_map): builder.call_circuit(x_qc) self.assertEqual(schedule, test_x_sched)