def test_insert_dd_ghz_everywhere(self): """Test DD gates even on initial idle spots. ┌───┐ ┌────────────────┐┌───┐┌────────────────┐┌───┐» q_0: ──────┤ H ├─────────■──┤ Delay(100[dt]) ├┤ Y ├┤ Delay(200[dt]) ├┤ Y ├» ┌─────┴───┴─────┐ ┌─┴─┐└────────────────┘└───┘└────────────────┘└───┘» q_1: ┤ Delay(50[dt]) ├─┤ X ├───────────────────────────────────────────■──» ├───────────────┴┐├───┤┌────────────────┐┌───┐┌────────────────┐┌─┴─┐» q_2: ┤ Delay(162[dt]) ├┤ Y ├┤ Delay(326[dt]) ├┤ Y ├┤ Delay(162[dt]) ├┤ X ├» ├────────────────┤├───┤├────────────────┤├───┤├────────────────┤└───┘» q_3: ┤ Delay(212[dt]) ├┤ Y ├┤ Delay(426[dt]) ├┤ Y ├┤ Delay(212[dt]) ├─────» └────────────────┘└───┘└────────────────┘└───┘└────────────────┘ » « ┌────────────────┐ «q_0: ┤ Delay(100[dt]) ├───────────────────────────────────────────── « ├───────────────┬┘┌───┐┌────────────────┐┌───┐┌───────────────┐ «q_1: ┤ Delay(50[dt]) ├─┤ Y ├┤ Delay(100[dt]) ├┤ Y ├┤ Delay(50[dt]) ├ « └───────────────┘ └───┘└────────────────┘└───┘└───────────────┘ «q_2: ────────■────────────────────────────────────────────────────── « ┌─┴─┐ «q_3: ──────┤ X ├──────────────────────────────────────────────────── « └───┘ """ dd_sequence = [YGate(), YGate()] pm = PassManager([ ALAPSchedule(self.durations), DynamicalDecoupling(self.durations, dd_sequence, skip_reset_qubits=False), ]) ghz4_dd = pm.run(self.ghz4) expected = self.ghz4.copy() expected = expected.compose(Delay(50), [1], front=True) expected = expected.compose(Delay(162), [2], front=True) expected = expected.compose(YGate(), [2], front=True) expected = expected.compose(Delay(326), [2], front=True) expected = expected.compose(YGate(), [2], front=True) expected = expected.compose(Delay(162), [2], front=True) expected = expected.compose(Delay(212), [3], front=True) expected = expected.compose(YGate(), [3], front=True) expected = expected.compose(Delay(426), [3], front=True) expected = expected.compose(YGate(), [3], front=True) expected = expected.compose(Delay(212), [3], front=True) expected = expected.compose(Delay(100), [0]) expected = expected.compose(YGate(), [0]) expected = expected.compose(Delay(200), [0]) expected = expected.compose(YGate(), [0]) expected = expected.compose(Delay(100), [0]) expected = expected.compose(Delay(50), [1]) expected = expected.compose(YGate(), [1]) expected = expected.compose(Delay(100), [1]) expected = expected.compose(YGate(), [1]) expected = expected.compose(Delay(50), [1]) self.assertEqual(ghz4_dd, expected)
def setUp(self): super().setUp() instruction_durations = InstructionDurations() instruction_durations.update( [ ("rz", (0,), 0), ("rz", (1,), 0), ("x", (0,), 160), ("x", (1,), 160), ("sx", (0,), 160), ("sx", (1,), 160), ("cx", (0, 1), 800), ("cx", (1, 0), 800), ("measure", None, 1600), ] ) self.time_conversion_pass = TimeUnitConversion(inst_durations=instruction_durations) # reproduce old behavior of 0.20.0 before #7655 # currently default write latency is 0 self.scheduling_pass = ALAPSchedule( durations=instruction_durations, clbit_write_latency=1600, conditional_latency=0, ) self.align_measure_pass = AlignMeasures(alignment=16)
def test_deprecated_align_measure(self): """Test if old AlignMeasures can be still used and warning is raised.""" circuit = QuantumCircuit(1, 1) circuit.x(0) circuit.delay(100) circuit.measure(0, 0) with self.assertWarns(PendingDeprecationWarning): pm_old = PassManager([ ALAPSchedule(durations=self.instruction_durations), AlignMeasures(alignment=16), ]) pm_new = PassManager([ ALAPSchedule(durations=self.instruction_durations), AlignMeasures(alignment=16), ]) self.assertEqual(pm_old.run(circuit), pm_new.run(circuit))
def test_insert_dd_bad_sequence(self): """Test DD raises when non-identity sequence is inserted.""" dd_sequence = [XGate(), YGate()] pm = PassManager([ ALAPSchedule(self.durations), DynamicalDecoupling(self.durations, dd_sequence), ]) with self.assertRaises(TranspilerError): pm.run(self.ghz4)
def test_active_reset_circuit(self, write_lat, cond_lat): """Test practical example of reset circuit. Because of the stimulus pulse overlap with the previous XGate on the q register, measure instruction is always triggered after XGate regardless of write latency. Thus only conditional latency matters in the scheduling. (input) ┌─┐ ┌───┐ ┌─┐ ┌───┐ ┌─┐ ┌───┐ q: ┤M├───┤ X ├───┤M├───┤ X ├───┤M├───┤ X ├─── └╥┘ └─╥─┘ └╥┘ └─╥─┘ └╥┘ └─╥─┘ ║ ┌────╨────┐ ║ ┌────╨────┐ ║ ┌────╨────┐ c: 1/═╩═╡ c_0=0x1 ╞═╩═╡ c_0=0x1 ╞═╩═╡ c_0=0x1 ╞ 0 └─────────┘ 0 └─────────┘ 0 └─────────┘ """ qc = QuantumCircuit(1, 1) qc.measure(0, 0) qc.x(0).c_if(0, 1) qc.measure(0, 0) qc.x(0).c_if(0, 1) qc.measure(0, 0) qc.x(0).c_if(0, 1) durations = InstructionDurations([("x", None, 100), ("measure", None, 1000)]) actual_asap = PassManager([ ASAPSchedule(durations, clbit_write_latency=write_lat, conditional_latency=cond_lat), PadDelay(), ]).run(qc) actual_alap = PassManager([ ALAPSchedule(durations, clbit_write_latency=write_lat, conditional_latency=cond_lat), PadDelay(), ]).run(qc) expected = QuantumCircuit(1, 1) expected.measure(0, 0) if cond_lat > 0: expected.delay(cond_lat, 0) expected.x(0).c_if(0, 1) expected.measure(0, 0) if cond_lat > 0: expected.delay(cond_lat, 0) expected.x(0).c_if(0, 1) expected.measure(0, 0) if cond_lat > 0: expected.delay(cond_lat, 0) expected.x(0).c_if(0, 1) self.assertEqual(expected, actual_asap) self.assertEqual(expected, actual_alap)
def test_hanh_echo_experiment_type(self): """Test Hahn echo experiment type circuit. (input) ┌────┐┌────────────────┐┌───┐┌────────────────┐┌────┐┌─┐ q_0: ┤ √X ├┤ Delay(100[dt]) ├┤ X ├┤ Delay(100[dt]) ├┤ √X ├┤M├ └────┘└────────────────┘└───┘└────────────────┘└────┘└╥┘ c: 1/══════════════════════════════════════════════════════╩═ 0 (output) ┌────┐┌────────────────┐┌───┐┌────────────────┐┌────┐┌──────────────┐┌─┐ q_0: ┤ √X ├┤ Delay(100[dt]) ├┤ X ├┤ Delay(100[dt]) ├┤ √X ├┤ Delay(8[dt]) ├┤M├ └────┘└────────────────┘└───┘└────────────────┘└────┘└──────────────┘└╥┘ c: 1/══════════════════════════════════════════════════════════════════════╩═ 0 This type of experiment doesn't change duration of interest (two in the middle). However induces slight delay less than alignment * dt before measurement. This might induce extra amplitude damping error. """ circuit = QuantumCircuit(1, 1) circuit.sx(0) circuit.delay(100, 0, unit="dt") circuit.x(0) circuit.delay(100, 0, unit="dt") circuit.sx(0) circuit.measure(0, 0) pm = PassManager([ # reproduce old behavior of 0.20.0 before #7655 # currently default write latency is 0 ALAPSchedule( durations=self.instruction_durations, clbit_write_latency=1600, conditional_latency=0, ), PadDelay(), AlignMeasures(alignment=16), ]) aligned_circuit = pm.run(circuit) ref_circuit = QuantumCircuit(1, 1) ref_circuit.sx(0) ref_circuit.delay(100, 0, unit="dt") ref_circuit.x(0) ref_circuit.delay(100, 0, unit="dt") ref_circuit.sx(0) ref_circuit.delay(8, 0, unit="dt") ref_circuit.measure(0, 0) self.assertEqual(aligned_circuit, ref_circuit)
def test_mid_circuit_measure(self): """Test circuit with mid circuit measurement. (input) ┌───┐┌────────────────┐┌─┐┌───────────────┐┌───┐┌────────────────┐┌─┐ q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├┤ Delay(10[dt]) ├┤ X ├┤ Delay(120[dt]) ├┤M├ └───┘└────────────────┘└╥┘└───────────────┘└───┘└────────────────┘└╥┘ c: 2/════════════════════════╩══════════════════════════════════════════╩═ 0 1 (output) ┌───┐┌────────────────┐┌─┐┌───────────────┐┌───┐┌────────────────┐┌─┐ q_0: ┤ X ├┤ Delay(112[dt]) ├┤M├┤ Delay(10[dt]) ├┤ X ├┤ Delay(134[dt]) ├┤M├ └───┘└────────────────┘└╥┘└───────────────┘└───┘└────────────────┘└╥┘ c: 2/════════════════════════╩══════════════════════════════════════════╩═ 0 1 Extra delay is always added to the existing delay right before the measurement. Delay after measurement is unchanged. """ circuit = QuantumCircuit(1, 2) circuit.x(0) circuit.delay(100, 0, unit="dt") circuit.measure(0, 0) circuit.delay(10, 0, unit="dt") circuit.x(0) circuit.delay(120, 0, unit="dt") circuit.measure(0, 1) pm = PassManager([ # reproduce old behavior of 0.20.0 before #7655 # currently default write latency is 0 ALAPSchedule( durations=self.instruction_durations, clbit_write_latency=1600, conditional_latency=0, ), PadDelay(), AlignMeasures(alignment=16), ]) aligned_circuit = pm.run(circuit) ref_circuit = QuantumCircuit(1, 2) ref_circuit.x(0) ref_circuit.delay(112, 0, unit="dt") ref_circuit.measure(0, 0) ref_circuit.delay(10, 0, unit="dt") ref_circuit.x(0) ref_circuit.delay(134, 0, unit="dt") ref_circuit.measure(0, 1) self.assertEqual(aligned_circuit, ref_circuit)
def test_insert_dd_ghz_one_qubit(self): """Test DD gates are inserted on only one qubit. ┌───┐ ┌────────────────┐ ┌───┐ » q_0: ──────┤ H ├─────────■──┤ Delay(100[dt]) ├──────┤ X ├───────» ┌─────┴───┴─────┐ ┌─┴─┐└────────────────┘┌─────┴───┴──────┐» q_1: ┤ Delay(50[dt]) ├─┤ X ├────────■─────────┤ Delay(300[dt]) ├» ├───────────────┴┐└───┘ ┌─┴─┐ └────────────────┘» q_2: ┤ Delay(750[dt]) ├───────────┤ X ├───────────────■─────────» ├────────────────┤ └───┘ ┌─┴─┐ » q_3: ┤ Delay(950[dt]) ├─────────────────────────────┤ X ├───────» └────────────────┘ └───┘ » meas: 4/═══════════════════════════════════════════════════════════» » « ┌────────────────┐┌───┐┌────────────────┐ ░ ┌─┐ « q_0: ┤ Delay(200[dt]) ├┤ X ├┤ Delay(100[dt]) ├─░─┤M├───────── « └────────────────┘└───┘└────────────────┘ ░ └╥┘┌─┐ « q_1: ──────────────────────────────────────────░──╫─┤M├────── « ░ ║ └╥┘┌─┐ « q_2: ──────────────────────────────────────────░──╫──╫─┤M├─── « ░ ║ ║ └╥┘┌─┐ « q_3: ──────────────────────────────────────────░──╫──╫──╫─┤M├ « ░ ║ ║ ║ └╥┘ «meas: 4/═════════════════════════════════════════════╩══╩══╩══╩═ « 0 1 2 3 """ dd_sequence = [XGate(), XGate()] pm = PassManager( [ ALAPSchedule(self.durations), DynamicalDecoupling(self.durations, dd_sequence, qubits=[0]), ] ) ghz4_dd = pm.run(self.ghz4.measure_all(inplace=False)) expected = self.ghz4.copy() expected = expected.compose(Delay(50), [1], front=True) expected = expected.compose(Delay(750), [2], front=True) expected = expected.compose(Delay(950), [3], front=True) expected = expected.compose(Delay(100), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(200), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(100), [0]) expected = expected.compose(Delay(300), [1]) expected.measure_all() self.assertEqual(ghz4_dd, expected)
def test_insert_midmeas_hahn_alap(self): """Test a single X gate as Hahn echo can absorb in the downstream circuit. global phase: 3π/2 ┌────────────────┐ ┌───┐ ┌────────────────┐» q_0: ────────■─────────┤ Delay(625[dt]) ├───────┤ X ├───────┤ Delay(625[dt]) ├» ┌─┴─┐ └────────────────┘┌──────┴───┴──────┐└────────────────┘» q_1: ──────┤ X ├───────────────■─────────┤ Delay(1000[dt]) ├────────■─────────» ┌─────┴───┴──────┐ ┌─┴─┐ └───────┬─┬───────┘ ┌─┴─┐ » q_2: ┤ Delay(700[dt]) ├──────┤ X ├───────────────┤M├──────────────┤ X ├───────» └────────────────┘ └───┘ └╥┘ └───┘ » c: 1/═════════════════════════════════════════════╩═══════════════════════════» 0 » « ┌───────────────┐ «q_0: ┤ U(0,π/2,-π/2) ├───■── « └───────────────┘ ┌─┴─┐ «q_1: ──────────────────┤ X ├ « ┌────────────────┐└───┘ «q_2: ┤ Delay(700[dt]) ├───── « └────────────────┘ «c: 1/═══════════════════════ """ dd_sequence = [XGate()] pm = PassManager([ ALAPSchedule(self.durations), DynamicalDecoupling(self.durations, dd_sequence) ]) midmeas_dd = pm.run(self.midmeas) combined_u = UGate(0, pi / 2, -pi / 2) expected = QuantumCircuit(3, 1) expected.cx(0, 1) expected.delay(625, 0) expected.x(0) expected.delay(625, 0) expected.compose(combined_u, [0], inplace=True) expected.delay(700, 2) expected.cx(1, 2) expected.delay(1000, 1) expected.measure(2, 0) expected.cx(1, 2) expected.cx(0, 1) expected.delay(700, 2) expected.global_phase = 4.71238898038469 self.assertEqual(midmeas_dd, expected) # check the absorption into U was done correctly self.assertEqual(Operator(combined_u), Operator(XGate()) & Operator(XGate()))
def test_insert_dd_ghz(self): """Test DD gates are inserted in correct spots. ┌───┐ ┌────────────────┐ ┌───┐ » q_0: ──────┤ H ├─────────■──┤ Delay(100[dt]) ├──────┤ X ├──────» ┌─────┴───┴─────┐ ┌─┴─┐└────────────────┘┌─────┴───┴─────┐» q_1: ┤ Delay(50[dt]) ├─┤ X ├────────■─────────┤ Delay(50[dt]) ├» ├───────────────┴┐└───┘ ┌─┴─┐ └───────────────┘» q_2: ┤ Delay(750[dt]) ├───────────┤ X ├───────────────■────────» ├────────────────┤ └───┘ ┌─┴─┐ » q_3: ┤ Delay(950[dt]) ├─────────────────────────────┤ X ├──────» └────────────────┘ └───┘ » « ┌────────────────┐ ┌───┐ ┌────────────────┐ «q_0: ┤ Delay(200[dt]) ├──────┤ X ├───────┤ Delay(100[dt]) ├───────────────── « └─────┬───┬──────┘┌─────┴───┴──────┐└─────┬───┬──────┘┌───────────────┐ «q_1: ──────┤ X ├───────┤ Delay(100[dt]) ├──────┤ X ├───────┤ Delay(50[dt]) ├ « └───┘ └────────────────┘ └───┘ └───────────────┘ «q_2: ─────────────────────────────────────────────────────────────────────── « «q_3: ─────────────────────────────────────────────────────────────────────── « """ dd_sequence = [XGate(), XGate()] pm = PassManager([ ALAPSchedule(self.durations), DynamicalDecoupling(self.durations, dd_sequence) ]) ghz4_dd = pm.run(self.ghz4) expected = self.ghz4.copy() expected = expected.compose(Delay(50), [1], front=True) expected = expected.compose(Delay(750), [2], front=True) expected = expected.compose(Delay(950), [3], front=True) expected = expected.compose(Delay(100), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(200), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(100), [0]) expected = expected.compose(Delay(50), [1]) expected = expected.compose(XGate(), [1]) expected = expected.compose(Delay(100), [1]) expected = expected.compose(XGate(), [1]) expected = expected.compose(Delay(50), [1]) self.assertEqual(ghz4_dd, expected)
def test_t1_experiment_type(self): """Test T1 experiment type circuit. (input) ┌───┐┌────────────────┐┌─┐ q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├ └───┘└────────────────┘└╥┘ c: 1/════════════════════════╩═ 0 (aligned) ┌───┐┌────────────────┐┌─┐ q_0: ┤ X ├┤ Delay(112[dt]) ├┤M├ └───┘└────────────────┘└╥┘ c: 1/════════════════════════╩═ 0 This type of experiment slightly changes delay duration of interest. However the quantization error should be less than alignment * dt. """ circuit = QuantumCircuit(1, 1) circuit.x(0) circuit.delay(100, 0, unit="dt") circuit.measure(0, 0) pm = PassManager([ # reproduce old behavior of 0.20.0 before #7655 # currently default write latency is 0 ALAPSchedule( durations=self.instruction_durations, clbit_write_latency=1600, conditional_latency=0, ), PadDelay(), AlignMeasures(alignment=16), ]) aligned_circuit = pm.run(circuit) ref_circuit = QuantumCircuit(1, 1) ref_circuit.x(0) ref_circuit.delay(112, 0, unit="dt") ref_circuit.measure(0, 0) self.assertEqual(aligned_circuit, ref_circuit)
def setUp(self): super().setUp() instruction_durations = InstructionDurations() instruction_durations.update([ ("rz", (0, ), 0), ("rz", (1, ), 0), ("x", (0, ), 160), ("x", (1, ), 160), ("sx", (0, ), 160), ("sx", (1, ), 160), ("cx", (0, 1), 800), ("cx", (1, 0), 800), ("measure", None, 1600), ]) self.time_conversion_pass = TimeUnitConversion( inst_durations=instruction_durations) self.scheduling_pass = ALAPSchedule(durations=instruction_durations) self.align_measure_pass = AlignMeasures(alignment=16)
def test_asymmetric_xy4_in_t2(self): """Test insertion of XY4 sequence with unbalanced spacing. global phase: π ┌───┐┌───┐┌────────────────┐┌───┐┌────────────────┐┌───┐┌────────────────┐» q_0: ┤ H ├┤ X ├┤ Delay(450[dt]) ├┤ Y ├┤ Delay(450[dt]) ├┤ X ├┤ Delay(450[dt]) ├» └───┘└───┘└────────────────┘└───┘└────────────────┘└───┘└────────────────┘» « ┌───┐┌────────────────┐┌───┐ «q_0: ┤ Y ├┤ Delay(450[dt]) ├┤ H ├ « └───┘└────────────────┘└───┘ """ dd_sequence = [XGate(), YGate()] * 2 spacing = [0] + [1 / 4] * 4 pm = PassManager( [ ALAPSchedule(self.durations), DynamicalDecoupling(self.durations, dd_sequence, spacing=spacing), ] ) t2 = QuantumCircuit(1) t2.h(0) t2.delay(2000, 0) t2.h(0) expected = QuantumCircuit(1) expected.h(0) expected.x(0) expected.delay(450, 0) expected.y(0) expected.delay(450, 0) expected.x(0) expected.delay(450, 0) expected.y(0) expected.delay(450, 0) expected.h(0) expected.global_phase = pi t2_dd = pm.run(t2) self.assertEqual(t2_dd, expected) # check global phase is correct self.assertEqual(Operator(t2), Operator(expected))
def test_alap_agree_with_reverse_asap_reverse(self): """Test if ALAP schedule agrees with doubly-reversed ASAP schedule.""" qc = QuantumCircuit(2) qc.h(0) qc.delay(500, 1) qc.cx(0, 1) qc.measure_all() durations = InstructionDurations([("h", 0, 200), ("cx", [0, 1], 700), ("measure", None, 1000)]) pm = PassManager(ALAPSchedule(durations)) alap_qc = pm.run(qc) pm = PassManager(ASAPSchedule(durations)) new_qc = pm.run(qc.reverse_ops()) new_qc = new_qc.reverse_ops() # pylint: disable=no-member new_qc.name = new_qc.name self.assertEqual(alap_qc, new_qc)
def test_dd_after_reset(self): """Test skip_reset_qubits option works. ┌─────────────────┐┌───┐┌────────────────┐┌───┐┌─────────────────┐» q_0: ─|0>─┤ Delay(1000[dt]) ├┤ H ├┤ Delay(190[dt]) ├┤ X ├┤ Delay(1710[dt]) ├» └─────────────────┘└───┘└────────────────┘└───┘└─────────────────┘» « ┌───┐┌───┐ «q_0: ┤ X ├┤ H ├ « └───┘└───┘ """ dd_sequence = [XGate(), XGate()] spacing = [0.1, 0.9] pm = PassManager( [ ALAPSchedule(self.durations), DynamicalDecoupling( self.durations, dd_sequence, spacing=spacing, skip_reset_qubits=True ), ] ) t2 = QuantumCircuit(1) t2.reset(0) t2.delay(1000) t2.h(0) t2.delay(2000, 0) t2.h(0) expected = QuantumCircuit(1) expected.reset(0) expected.delay(1000) expected.h(0) expected.delay(190, 0) expected.x(0) expected.delay(1710, 0) expected.x(0) expected.h(0) t2_dd = pm.run(t2) self.assertEqual(t2_dd, expected)
def test_dd_with_calibrations_with_parameters(self, param_value): """Check that calibrations in a circuit with parameters work fine.""" circ = QuantumCircuit(2) circ.x(0) circ.cx(0, 1) circ.rx(param_value, 1) rx_duration = int(param_value * 1000) with pulse.build() as rx: pulse.play(pulse.Gaussian(rx_duration, 0.1, rx_duration // 4), pulse.DriveChannel(1)) circ.add_calibration("rx", (1,), rx, params=[param_value]) durations = InstructionDurations([("x", None, 100), ("cx", None, 300)]) dd_sequence = [XGate(), XGate()] pm = PassManager([ALAPSchedule(durations), DynamicalDecoupling(durations, dd_sequence)]) self.assertEqual(pm.run(circ).duration, rx_duration + 100 + 300)
def setup(self, n_qubits, depth): seed = 42 self.circuit = random_circuit(n_qubits, depth, measure=True, conditional=True, reset=True, seed=seed, max_operands=2) self.basis_gates = ['rz', 'sx', 'x', 'cx', 'id', 'reset'] self.cmap = [[0, 1], [1, 0], [1, 2], [1, 6], [2, 1], [2, 3], [3, 2], [3, 4], [3, 8], [4, 3], [5, 6], [5, 10], [6, 1], [6, 5], [6, 7], [7, 6], [7, 8], [7, 12], [8, 3], [8, 7], [8, 9], [9, 8], [9, 14], [10, 5], [10, 11], [11, 10], [11, 12], [11, 16], [12, 7], [12, 11], [12, 13], [13, 12], [13, 14], [13, 18], [14, 9], [14, 13], [15, 16], [16, 11], [16, 15], [16, 17], [17, 16], [17, 18], [18, 13], [18, 17], [18, 19], [19, 18]] self.coupling_map = CouplingMap(self.cmap) self.transpiled_circuit = transpile(self.circuit, basis_gates=self.basis_gates, coupling_map=self.coupling_map, optimization_level=1) self.dag = circuit_to_dag(self.transpiled_circuit) self.durations = InstructionDurations([ ("rz", None, 0), ("id", None, 160), ("sx", None, 160), ("x", None, 160), ("cx", None, 800), ("measure", None, 3200), ("reset", None, 3600), ], dt=1e-9) self.timed_dag = TimeUnitConversion(self.durations).run(self.dag) _pass = ALAPSchedule(self.durations) _pass.property_set['time_unit'] = "dt" self.scheduled_dag = _pass.run(self.timed_dag)
def level_0_pass_manager( pass_manager_config: PassManagerConfig) -> PassManager: """Level 0 pass manager: no explicit optimization other than mapping to backend. This pass manager applies the user-given initial layout. If none is given, a trivial layout consisting of mapping the i-th virtual qubit to the i-th physical qubit is used. Any unused physical qubit is allocated as ancilla space. The pass manager then unrolls the circuit to the desired basis, and transforms the circuit to match the coupling map. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 0 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or 'trivial' routing_method = pass_manager_config.routing_method or 'stochastic' translation_method = pass_manager_config.translation_method or 'translator' scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties # 1. Choose an initial layout if not set by user (default: trivial layout) _given_layout = SetLayout(initial_layout) def _choose_layout_condition(property_set): return not property_set['layout'] if layout_method == 'trivial': _choose_layout = TrivialLayout(coupling_map) elif layout_method == 'dense': _choose_layout = DenseLayout(coupling_map, backend_properties) elif layout_method == 'noise_adaptive': _choose_layout = NoiseAdaptiveLayout(backend_properties) elif layout_method == 'sabre': _choose_layout = SabreLayout(coupling_map, max_iterations=1, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) # 2. Extend dag/layout with ancillas using the full coupling map _embed = [ FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout() ] # 3. Decompose so only 1-qubit and 2-qubit gates remain _unroll3q = Unroll3qOrMore() # 4. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set['is_swap_mapped'] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == 'basic': _swap += [BasicSwap(coupling_map)] elif routing_method == 'stochastic': _swap += [ StochasticSwap(coupling_map, trials=20, seed=seed_transpiler) ] elif routing_method == 'lookahead': _swap += [LookaheadSwap(coupling_map, search_depth=2, search_width=2)] elif routing_method == 'sabre': _swap += [ SabreSwap(coupling_map, heuristic='basic', seed=seed_transpiler) ] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 5. Unroll to the basis if translation_method == 'unroller': _unroll = [Unroller(basis_gates)] elif translation_method == 'translator': from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [ UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates) ] elif translation_method == 'synthesis': _unroll = [ Unroll3qOrMore(), Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis(basis_gates), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 6. Fix any bad CX directions _direction_check = [CheckCXDirection(coupling_map)] def _direction_condition(property_set): return not property_set['is_direction_mapped'] _direction = [CXDirection(coupling_map)] # 7. Schedule the circuit only when scheduling_method is supplied if scheduling_method: _scheduling = [TimeUnitAnalysis(instruction_durations)] if scheduling_method in {'alap', 'as_late_as_possible'}: _scheduling += [ALAPSchedule(instruction_durations)] elif scheduling_method in {'asap', 'as_soon_as_possible'}: _scheduling += [ASAPSchedule(instruction_durations)] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # Build pass manager pm0 = PassManager() if coupling_map: pm0.append(_given_layout) pm0.append(_choose_layout, condition=_choose_layout_condition) pm0.append(_embed) pm0.append(_unroll3q) pm0.append(_swap_check) pm0.append(_swap, condition=_swap_condition) pm0.append(_unroll) if coupling_map and not coupling_map.is_symmetric: pm0.append(_direction_check) pm0.append(_direction, condition=_direction_condition) if scheduling_method: pm0.append(_scheduling) return pm0
def level_3_pass_manager(pass_manager_config: PassManagerConfig) -> PassManager: """Level 3 pass manager: heavy optimization by noise adaptive qubit mapping and gate cancellation using commutativity rules and unitary synthesis. This pass manager applies the user-given initial layout. If none is given, a search for a perfect layout (i.e. one that satisfies all 2-qubit interactions) is conducted. If no such layout is found, and device calibration information is available, the circuit is mapped to the qubits with best readouts and to CX gates with highest fidelity. The pass manager then transforms the circuit to match the coupling constraints. It is then unrolled to the basis, and any flipped cx directions are fixed. Finally, optimizations in the form of commutative gate cancellation, resynthesis of two-qubit unitary blocks, and redundant reset removal are performed. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 3 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates inst_map = pass_manager_config.inst_map coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or "sabre" routing_method = pass_manager_config.routing_method or "sabre" translation_method = pass_manager_config.translation_method or "translator" scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties approximation_degree = pass_manager_config.approximation_degree unitary_synthesis_method = pass_manager_config.unitary_synthesis_method timing_constraints = pass_manager_config.timing_constraints or TimingConstraints() unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config target = pass_manager_config.target # 1. Unroll to 1q or 2q gates _unroll3q = [ # Use unitary synthesis for basis aware decomposition of UnitaryGates UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, min_qubits=3, ), Unroll3qOrMore(), ] # 2. Layout on good qubits if calibration info available, otherwise on dense links _given_layout = SetLayout(initial_layout) def _choose_layout_condition(property_set): # layout hasn't been set yet return not property_set["layout"] def _csp_not_found_match(property_set): # If a layout hasn't been set by the time we run csp we need to run layout if property_set["layout"] is None: return True # if CSP layout stopped for any reason other than solution found we need # to run layout since CSP didn't converge. if ( property_set["CSPLayout_stop_reason"] is not None and property_set["CSPLayout_stop_reason"] != "solution found" ): return True return False # 2a. If layout method is not set, first try a trivial layout _choose_layout_0 = ( [] if pass_manager_config.layout_method else [ TrivialLayout(coupling_map), Layout2qDistance(coupling_map, property_name="trivial_layout_score"), ] ) # 2b. If trivial layout wasn't perfect (ie no swaps are needed) then try # using CSP layout to find a perfect layout _choose_layout_1 = ( [] if pass_manager_config.layout_method else CSPLayout(coupling_map, call_limit=10000, time_limit=60, seed=seed_transpiler) ) def _trivial_not_perfect(property_set): # Verify that a trivial layout is perfect. If trivial_layout_score > 0 # the layout is not perfect. The layout property set is unconditionally # set by trivial layout so we clear that before running CSP if property_set["trivial_layout_score"] is not None: if property_set["trivial_layout_score"] != 0: return True return False # 2c. if CSP didn't converge on a solution use layout_method (dense). if layout_method == "trivial": _choose_layout_2 = TrivialLayout(coupling_map) elif layout_method == "dense": _choose_layout_2 = DenseLayout(coupling_map, backend_properties) elif layout_method == "noise_adaptive": _choose_layout_2 = NoiseAdaptiveLayout(backend_properties) elif layout_method == "sabre": _choose_layout_2 = SabreLayout(coupling_map, max_iterations=4, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) # 3. Extend dag/layout with ancillas using the full coupling map _embed = [FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout()] # 4. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set["is_swap_mapped"] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == "basic": _swap += [BasicSwap(coupling_map)] elif routing_method == "stochastic": _swap += [StochasticSwap(coupling_map, trials=200, seed=seed_transpiler)] elif routing_method == "lookahead": _swap += [LookaheadSwap(coupling_map, search_depth=5, search_width=6)] elif routing_method == "sabre": _swap += [SabreSwap(coupling_map, heuristic="decay", seed=seed_transpiler)] elif routing_method == "none": _swap += [ Error( msg=( "No routing method selected, but circuit is not routed to device. " "CheckMap Error: {check_map_msg}" ), action="raise", ) ] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 5. Unroll to the basis if translation_method == "unroller": _unroll = [Unroller(basis_gates)] elif translation_method == "translator": from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [ UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, plugin_config=unitary_synthesis_plugin_config, method=unitary_synthesis_method, ), UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates, target), ] elif translation_method == "synthesis": _unroll = [ UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, min_qubits=3, ), Unroll3qOrMore(), Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, ), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 6. Fix any CX direction mismatch _direction_check = [CheckGateDirection(coupling_map, target)] def _direction_condition(property_set): return not property_set["is_direction_mapped"] _direction = [GateDirection(coupling_map, target)] # 8. Optimize iteratively until no more change in depth. Removes useless gates # after reset and before measure, commutes gates and optimizes contiguous blocks. _depth_check = [Depth(), FixedPoint("depth")] def _opt_control(property_set): return not property_set["depth_fixed_point"] _reset = [RemoveResetInZeroState()] _meas = [OptimizeSwapBeforeMeasure(), RemoveDiagonalGatesBeforeMeasure()] _opt = [ Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, ), Optimize1qGatesDecomposition(basis_gates), CommutativeCancellation(), ] # 9. Unify all durations (either SI, or convert to dt if known) # Schedule the circuit only when scheduling_method is supplied _time_unit_setup = [ContainsInstruction("delay")] _time_unit_conversion = [TimeUnitConversion(instruction_durations)] def _contains_delay(property_set): return property_set["contains_delay"] _scheduling = [] if scheduling_method: _scheduling += _time_unit_conversion if scheduling_method in {"alap", "as_late_as_possible"}: _scheduling += [ALAPSchedule(instruction_durations)] elif scheduling_method in {"asap", "as_soon_as_possible"}: _scheduling += [ASAPSchedule(instruction_durations)] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # 10. Call measure alignment. Should come after scheduling. if ( timing_constraints.granularity != 1 or timing_constraints.min_length != 1 or timing_constraints.acquire_alignment != 1 ): _alignments = [ ValidatePulseGates( granularity=timing_constraints.granularity, min_length=timing_constraints.min_length ), AlignMeasures(alignment=timing_constraints.acquire_alignment), ] else: _alignments = [] # Build pass manager pm3 = PassManager() pm3.append(_unroll3q) pm3.append(_reset + _meas) if coupling_map or initial_layout: pm3.append(_given_layout) pm3.append(_choose_layout_0, condition=_choose_layout_condition) pm3.append(_choose_layout_1, condition=_trivial_not_perfect) pm3.append(_choose_layout_2, condition=_csp_not_found_match) pm3.append(_embed) pm3.append(_swap_check) pm3.append(_swap, condition=_swap_condition) pm3.append(_unroll) if (coupling_map and not coupling_map.is_symmetric) or ( target is not None and target.get_non_global_operation_names(strict_direction=True) ): pm3.append(_direction_check) pm3.append(_direction, condition=_direction_condition) pm3.append(_reset) # For transpiling to a target we need to run GateDirection in the # optimization loop to correct for incorrect directions that might be # inserted by UnitarySynthesis which is direction aware but only via # the coupling map which with a target doesn't give a full picture if target is not None: pm3.append(_depth_check + _opt + _unroll + _direction, do_while=_opt_control) else: pm3.append(_depth_check + _opt + _unroll, do_while=_opt_control) else: pm3.append(_reset) pm3.append(_depth_check + _opt + _unroll, do_while=_opt_control) if inst_map and inst_map.has_custom_gate(): pm3.append(PulseGates(inst_map=inst_map)) if scheduling_method: pm3.append(_scheduling) elif instruction_durations: pm3.append(_time_unit_setup) pm3.append(_time_unit_conversion, condition=_contains_delay) pm3.append(_alignments) return pm3
def level_3_pass_manager( pass_manager_config: PassManagerConfig) -> PassManager: """Level 3 pass manager: heavy optimization by noise adaptive qubit mapping and gate cancellation using commutativity rules and unitary synthesis. This pass manager applies the user-given initial layout. If none is given, a search for a perfect layout (i.e. one that satisfies all 2-qubit interactions) is conducted. If no such layout is found, and device calibration information is available, the circuit is mapped to the qubits with best readouts and to CX gates with highest fidelity. The pass manager then transforms the circuit to match the coupling constraints. It is then unrolled to the basis, and any flipped cx directions are fixed. Finally, optimizations in the form of commutative gate cancellation, resynthesis of two-qubit unitary blocks, and redundant reset removal are performed. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 3 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or 'dense' routing_method = pass_manager_config.routing_method or 'stochastic' translation_method = pass_manager_config.translation_method or 'translator' scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties # 1. Unroll to 1q or 2q gates _unroll3q = Unroll3qOrMore() # 2. Layout on good qubits if calibration info available, otherwise on dense links _given_layout = SetLayout(initial_layout) def _choose_layout_condition(property_set): return not property_set['layout'] _choose_layout_1 = [] if pass_manager_config.layout_method \ else CSPLayout(coupling_map, call_limit=10000, time_limit=60, seed=seed_transpiler) if layout_method == 'trivial': _choose_layout_2 = TrivialLayout(coupling_map) elif layout_method == 'dense': _choose_layout_2 = DenseLayout(coupling_map, backend_properties) elif layout_method == 'noise_adaptive': _choose_layout_2 = NoiseAdaptiveLayout(backend_properties) elif layout_method == 'sabre': _choose_layout_2 = SabreLayout(coupling_map, max_iterations=4, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) # 3. Extend dag/layout with ancillas using the full coupling map _embed = [ FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout() ] # 4. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set['is_swap_mapped'] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == 'basic': _swap += [BasicSwap(coupling_map)] elif routing_method == 'stochastic': _swap += [ StochasticSwap(coupling_map, trials=200, seed=seed_transpiler) ] elif routing_method == 'lookahead': _swap += [LookaheadSwap(coupling_map, search_depth=5, search_width=6)] elif routing_method == 'sabre': _swap += [ SabreSwap(coupling_map, heuristic='decay', seed=seed_transpiler) ] elif routing_method == 'none': _swap += [ Error( msg= 'No routing method selected, but circuit is not routed to device. ' 'CheckMap Error: {check_map_msg}', action='raise') ] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 5. Unroll to the basis if translation_method == 'unroller': _unroll = [Unroller(basis_gates)] elif translation_method == 'translator': from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [ UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates) ] elif translation_method == 'synthesis': _unroll = [ Unroll3qOrMore(), Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis(basis_gates), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 6. Fix any CX direction mismatch _direction_check = [CheckCXDirection(coupling_map)] def _direction_condition(property_set): return not property_set['is_direction_mapped'] _direction = [CXDirection(coupling_map)] # 8. Optimize iteratively until no more change in depth. Removes useless gates # after reset and before measure, commutes gates and optimizes contiguous blocks. _depth_check = [Depth(), FixedPoint('depth')] def _opt_control(property_set): return not property_set['depth_fixed_point'] _reset = [RemoveResetInZeroState()] _meas = [OptimizeSwapBeforeMeasure(), RemoveDiagonalGatesBeforeMeasure()] _opt = [ Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis(basis_gates), Optimize1qGatesDecomposition(basis_gates), CommutativeCancellation(), ] # Schedule the circuit only when scheduling_method is supplied if scheduling_method: _scheduling = [TimeUnitAnalysis(instruction_durations)] if scheduling_method in {'alap', 'as_late_as_possible'}: _scheduling += [ALAPSchedule(instruction_durations)] elif scheduling_method in {'asap', 'as_soon_as_possible'}: _scheduling += [ASAPSchedule(instruction_durations)] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # Build pass manager pm3 = PassManager() pm3.append(_unroll3q) pm3.append(_reset + _meas) if coupling_map or initial_layout: pm3.append(_given_layout) pm3.append(_choose_layout_1, condition=_choose_layout_condition) pm3.append(_choose_layout_2, condition=_choose_layout_condition) pm3.append(_embed) pm3.append(_swap_check) pm3.append(_swap, condition=_swap_condition) pm3.append(_unroll) pm3.append(_depth_check + _opt + _unroll, do_while=_opt_control) if coupling_map and not coupling_map.is_symmetric: pm3.append(_direction_check) pm3.append(_direction, condition=_direction_condition) pm3.append(_reset) if scheduling_method: pm3.append(_scheduling) return pm3
def level_2_pass_manager(pass_manager_config: PassManagerConfig) -> PassManager: """Level 2 pass manager: medium optimization by initial layout selection and gate cancellation using commutativity rules. This pass manager applies the user-given initial layout. If none is given, a search for a perfect layout (i.e. one that satisfies all 2-qubit interactions) is conducted. If no such layout is found, qubits are laid out on the most densely connected subset which also exhibits the best gate fidelitites. The pass manager then transforms the circuit to match the coupling constraints. It is then unrolled to the basis, and any flipped cx directions are fixed. Finally, optimizations in the form of commutative gate cancellation and redundant reset removal are performed. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 2 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or 'dense' routing_method = pass_manager_config.routing_method or 'stochastic' translation_method = pass_manager_config.translation_method or 'translator' scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties # 1. Search for a perfect layout, or choose a dense layout, if no layout given _given_layout = SetLayout(initial_layout) def _choose_layout_condition(property_set): return not property_set['layout'] _choose_layout_1 = CSPLayout(coupling_map, call_limit=1000, time_limit=10) if layout_method == 'trivial': _choose_layout_2 = TrivialLayout(coupling_map) elif layout_method == 'dense': _choose_layout_2 = DenseLayout(coupling_map, backend_properties) elif layout_method == 'noise_adaptive': _choose_layout_2 = NoiseAdaptiveLayout(backend_properties) elif layout_method == 'sabre': _choose_layout_2 = SabreLayout(coupling_map, max_iterations=2, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) # 2. Extend dag/layout with ancillas using the full coupling map _embed = [FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout()] # 3. Unroll to 1q or 2q gates _unroll3q = Unroll3qOrMore() # 4. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set['is_swap_mapped'] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == 'basic': _swap += [BasicSwap(coupling_map)] elif routing_method == 'stochastic': _swap += [StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)] elif routing_method == 'lookahead': _swap += [LookaheadSwap(coupling_map, search_depth=5, search_width=5)] elif routing_method == 'sabre': _swap += [SabreSwap(coupling_map, heuristic='decay', seed=seed_transpiler)] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 5. Unroll to the basis if translation_method == 'unroller': _unroll = [Unroller(basis_gates)] elif translation_method == 'translator': from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates)] elif translation_method == 'synthesis': _unroll = [ Unroll3qOrMore(), Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis(basis_gates), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 6. Fix any bad CX directions _direction_check = [CheckCXDirection(coupling_map)] def _direction_condition(property_set): return not property_set['is_direction_mapped'] _direction = [CXDirection(coupling_map)] # 7. Remove zero-state reset _reset = RemoveResetInZeroState() # 8. 1q rotation merge and commutative cancellation iteratively until no more change in depth _depth_check = [Depth(), FixedPoint('depth')] def _opt_control(property_set): return not property_set['depth_fixed_point'] _opt = [Optimize1qGates(basis_gates), CommutativeCancellation()] # 9. Schedule the circuit only when scheduling_method is supplied if scheduling_method: _scheduling = [TimeUnitAnalysis(instruction_durations)] if scheduling_method in {'alap', 'as_late_as_possible'}: _scheduling += [ALAPSchedule(instruction_durations)] elif scheduling_method in {'asap', 'as_soon_as_possible'}: _scheduling += [ASAPSchedule(instruction_durations)] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # Build pass manager pm2 = PassManager() if coupling_map: pm2.append(_given_layout) pm2.append(_choose_layout_1, condition=_choose_layout_condition) pm2.append(_choose_layout_2, condition=_choose_layout_condition) pm2.append(_embed) pm2.append(_unroll3q) pm2.append(_swap_check) pm2.append(_swap, condition=_swap_condition) pm2.append(_unroll) if coupling_map and not coupling_map.is_symmetric: pm2.append(_direction_check) pm2.append(_direction, condition=_direction_condition) pm2.append(_reset) pm2.append(_depth_check + _opt, do_while=_opt_control) if scheduling_method: pm2.append(_scheduling) return pm2
def test_random_complicated_circuit(self): """Test scheduling complicated circuit with control flow. (input) ┌────────────────┐ ┌───┐ ░ ┌───┐ » q_0: ┤ Delay(100[dt]) ├───┤ X ├────░──────────────────┤ X ├───» └────────────────┘ └─╥─┘ ░ ┌───┐ └─╥─┘ » q_1: ───────────────────────╫──────░───────┤ X ├────────╫─────» ║ ░ ┌─┐ └─╥─┘ ║ » q_2: ───────────────────────╫──────░─┤M├─────╫──────────╫─────» ┌────╨────┐ ░ └╥┘┌────╨────┐┌────╨────┐» c: 1/══════════════════╡ c_0=0x1 ╞════╩═╡ c_0=0x0 ╞╡ c_0=0x0 ╞» └─────────┘ 0 └─────────┘└─────────┘» « ┌────────────────┐┌───┐ «q_0: ┤ Delay(300[dt]) ├┤ X ├─────■───── « └────────────────┘└───┘ ┌─┴─┐ «q_1: ────────■─────────────────┤ X ├─── « ┌─┴─┐ ┌─┐ └─╥─┘ «q_2: ──────┤ X ├────────┤M├──────╫───── « └───┘ └╥┘ ┌────╨────┐ «c: 1/════════════════════╩══╡ c_0=0x0 ╞ « 0 └─────────┘ (ASAP scheduled) duration = 2800 dt ┌────────────────┐┌────────────────┐ ┌───┐ ░ ┌─────────────────┐» q_0: ┤ Delay(100[dt]) ├┤ Delay(100[dt]) ├───┤ X ├────░─┤ Delay(1400[dt]) ├» ├────────────────┤└────────────────┘ └─╥─┘ ░ ├─────────────────┤» q_1: ┤ Delay(300[dt]) ├───────────────────────╫──────░─┤ Delay(1200[dt]) ├» ├────────────────┤ ║ ░ └───────┬─┬───────┘» q_2: ┤ Delay(300[dt]) ├───────────────────────╫──────░─────────┤M├────────» └────────────────┘ ┌────╨────┐ ░ └╥┘ » c: 1/════════════════════════════════════╡ c_0=0x1 ╞════════════╩═════════» └─────────┘ 0 » « ┌───┐ ┌────────────────┐» «q_0: ────────────────────────────────┤ X ├───┤ Delay(300[dt]) ├» « ┌───┐ └─╥─┘ └────────────────┘» «q_1: ───┤ X ├──────────────────────────╫─────────────■─────────» « └─╥─┘ ┌────────────────┐ ║ ┌─┴─┐ » «q_2: ─────╫─────┤ Delay(300[dt]) ├─────╫───────────┤ X ├───────» « ┌────╨────┐└────────────────┘┌────╨────┐ └───┘ » «c: 1/╡ c_0=0x0 ╞══════════════════╡ c_0=0x0 ╞══════════════════» « └─────────┘ └─────────┘ » « ┌───┐ ┌────────────────┐ «q_0: ──────┤ X ├────────────■─────┤ Delay(700[dt]) ├ « ┌─────┴───┴──────┐ ┌─┴─┐ ├────────────────┤ «q_1: ┤ Delay(400[dt]) ├───┤ X ├───┤ Delay(700[dt]) ├ « ├────────────────┤ └─╥─┘ └──────┬─┬───────┘ «q_2: ┤ Delay(300[dt]) ├─────╫────────────┤M├──────── « └────────────────┘┌────╨────┐ └╥┘ «c: 1/══════════════════╡ c_0=0x0 ╞════════╩═════════ « └─────────┘ 0 (ALAP scheduled) duration = 3100 ┌────────────────┐┌────────────────┐ ┌───┐ ░ ┌─────────────────┐» q_0: ┤ Delay(100[dt]) ├┤ Delay(100[dt]) ├───┤ X ├────░─┤ Delay(1400[dt]) ├» ├────────────────┤└────────────────┘ └─╥─┘ ░ ├─────────────────┤» q_1: ┤ Delay(300[dt]) ├───────────────────────╫──────░─┤ Delay(1200[dt]) ├» ├────────────────┤ ║ ░ └───────┬─┬───────┘» q_2: ┤ Delay(300[dt]) ├───────────────────────╫──────░─────────┤M├────────» └────────────────┘ ┌────╨────┐ ░ └╥┘ » c: 1/════════════════════════════════════╡ c_0=0x1 ╞════════════╩═════════» └─────────┘ 0 » « ┌───┐ ┌────────────────┐» «q_0: ────────────────────────────────┤ X ├───┤ Delay(300[dt]) ├» « ┌───┐ ┌────────────────┐ └─╥─┘ └────────────────┘» «q_1: ───┤ X ├───┤ Delay(300[dt]) ├─────╫─────────────■─────────» « └─╥─┘ ├────────────────┤ ║ ┌─┴─┐ » «q_2: ─────╫─────┤ Delay(600[dt]) ├─────╫───────────┤ X ├───────» « ┌────╨────┐└────────────────┘┌────╨────┐ └───┘ » «c: 1/╡ c_0=0x0 ╞══════════════════╡ c_0=0x0 ╞══════════════════» « └─────────┘ └─────────┘ » « ┌───┐ ┌────────────────┐ «q_0: ──────┤ X ├────────────■─────┤ Delay(700[dt]) ├ « ┌─────┴───┴──────┐ ┌─┴─┐ ├────────────────┤ «q_1: ┤ Delay(100[dt]) ├───┤ X ├───┤ Delay(700[dt]) ├ « └──────┬─┬───────┘ └─╥─┘ └────────────────┘ «q_2: ───────┤M├─────────────╫─────────────────────── « └╥┘ ┌────╨────┐ «c: 1/════════╩═════════╡ c_0=0x0 ╞══════════════════ « 0 └─────────┘ """ qc = QuantumCircuit(3, 1) qc.delay(100, 0) qc.x(0).c_if(0, 1) qc.barrier() qc.measure(2, 0) qc.x(1).c_if(0, 0) qc.x(0).c_if(0, 0) qc.delay(300, 0) qc.cx(1, 2) qc.x(0) qc.cx(0, 1).c_if(0, 0) qc.measure(2, 0) durations = InstructionDurations([("x", None, 100), ("measure", None, 1000), ("cx", None, 200)]) actual_asap = PassManager( ASAPSchedule(durations, clbit_write_latency=100, conditional_latency=200)).run(qc) actual_alap = PassManager( ALAPSchedule(durations, clbit_write_latency=100, conditional_latency=200)).run(qc) expected_asap = QuantumCircuit(3, 1) expected_asap.delay(100, 0) expected_asap.delay(100, 0) # due to conditional latency of 200dt expected_asap.delay(300, 1) expected_asap.delay(300, 2) expected_asap.x(0).c_if(0, 1) expected_asap.barrier() expected_asap.delay(1400, 0) expected_asap.delay(1200, 1) expected_asap.measure(2, 0) expected_asap.x(1).c_if(0, 0) expected_asap.x(0).c_if(0, 0) expected_asap.delay(300, 0) expected_asap.x(0) expected_asap.delay(300, 2) expected_asap.cx(1, 2) expected_asap.delay(400, 1) expected_asap.cx(0, 1).c_if(0, 0) expected_asap.delay(700, 0) # creg is released at t0 of cx(0,1).c_if(0,0) expected_asap.delay( 700, 1 ) # no creg write until 100dt. thus measure can move left by 300dt. expected_asap.delay(300, 2) expected_asap.measure(2, 0) self.assertEqual(expected_asap, actual_asap) self.assertEqual(actual_asap.duration, 3100) expected_alap = QuantumCircuit(3, 1) expected_alap.delay(100, 0) expected_alap.delay(100, 0) # due to conditional latency of 200dt expected_alap.delay(300, 1) expected_alap.delay(300, 2) expected_alap.x(0).c_if(0, 1) expected_alap.barrier() expected_alap.delay(1400, 0) expected_alap.delay(1200, 1) expected_alap.measure(2, 0) expected_alap.x(1).c_if(0, 0) expected_alap.x(0).c_if(0, 0) expected_alap.delay(300, 0) expected_alap.x(0) expected_alap.delay(300, 1) expected_alap.delay(600, 2) expected_alap.cx(1, 2) expected_alap.delay(100, 1) expected_alap.cx(0, 1).c_if(0, 0) expected_alap.measure(2, 0) expected_alap.delay(700, 0) expected_alap.delay(700, 1) self.assertEqual(expected_alap, actual_alap) self.assertEqual(actual_alap.duration, 3100)
def level_1_pass_manager( pass_manager_config: PassManagerConfig) -> PassManager: """Level 1 pass manager: light optimization by simple adjacent gate collapsing. This pass manager applies the user-given initial layout. If none is given, and a trivial layout (i-th virtual -> i-th physical) makes the circuit fit the coupling map, that is used. Otherwise, the circuit is mapped to the most densely connected coupling subgraph, and swaps are inserted to map. Any unused physical qubit is allocated as ancilla space. The pass manager then unrolls the circuit to the desired basis, and transforms the circuit to match the coupling map. Finally, optimizations in the form of adjacent gate collapse and redundant reset removal are performed. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 1 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates inst_map = pass_manager_config.inst_map coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or "dense" routing_method = pass_manager_config.routing_method or "stochastic" translation_method = pass_manager_config.translation_method or "translator" scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties approximation_degree = pass_manager_config.approximation_degree unitary_synthesis_method = pass_manager_config.unitary_synthesis_method unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config timing_constraints = pass_manager_config.timing_constraints or TimingConstraints( ) target = pass_manager_config.target # 1. Use trivial layout if no layout given _given_layout = SetLayout(initial_layout) _choose_layout_and_score = [ TrivialLayout(coupling_map), Layout2qDistance(coupling_map, property_name="trivial_layout_score"), ] def _choose_layout_condition(property_set): return not property_set["layout"] # 2. Decompose so only 1-qubit and 2-qubit gates remain _unroll3q = [ # Use unitary synthesis for basis aware decomposition of UnitaryGates UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, method=unitary_synthesis_method, min_qubits=3, plugin_config=unitary_synthesis_plugin_config, ), Unroll3qOrMore(), ] # 3. Use a better layout on densely connected qubits, if circuit needs swaps if layout_method == "trivial": _improve_layout = TrivialLayout(coupling_map) elif layout_method == "dense": _improve_layout = DenseLayout(coupling_map, backend_properties) elif layout_method == "noise_adaptive": _improve_layout = NoiseAdaptiveLayout(backend_properties) elif layout_method == "sabre": _improve_layout = SabreLayout(coupling_map, max_iterations=2, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) def _not_perfect_yet(property_set): return (property_set["trivial_layout_score"] is not None and property_set["trivial_layout_score"] != 0) # 4. Extend dag/layout with ancillas using the full coupling map _embed = [ FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout() ] # 5. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set["is_swap_mapped"] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == "basic": _swap += [BasicSwap(coupling_map)] elif routing_method == "stochastic": _swap += [ StochasticSwap(coupling_map, trials=20, seed=seed_transpiler) ] elif routing_method == "lookahead": _swap += [LookaheadSwap(coupling_map, search_depth=4, search_width=4)] elif routing_method == "sabre": _swap += [ SabreSwap(coupling_map, heuristic="lookahead", seed=seed_transpiler) ] elif routing_method == "none": _swap += [ Error( msg= ("No routing method selected, but circuit is not routed to device. " "CheckMap Error: {check_map_msg}"), action="raise", ) ] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 6. Unroll to the basis if translation_method == "unroller": _unroll = [Unroller(basis_gates)] elif translation_method == "translator": from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [ # Use unitary synthesis for basis aware decomposition of UnitaryGates before # custom unrolling UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, method=unitary_synthesis_method, backend_props=backend_properties, plugin_config=unitary_synthesis_plugin_config, ), UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates, target), ] elif translation_method == "synthesis": _unroll = [ # Use unitary synthesis for basis aware decomposition of UnitaryGates before # collection UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, method=unitary_synthesis_method, backend_props=backend_properties, min_qubits=3, ), Unroll3qOrMore(), Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, method=unitary_synthesis_method, backend_props=backend_properties, plugin_config=unitary_synthesis_plugin_config, ), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 7. Fix any bad CX directions _direction_check = [CheckGateDirection(coupling_map, target)] def _direction_condition(property_set): return not property_set["is_direction_mapped"] _direction = [GateDirection(coupling_map, target)] # 8. Remove zero-state reset _reset = RemoveResetInZeroState() # 9. Merge 1q rotations and cancel CNOT gates iteratively until no more change in depth _depth_check = [Depth(), FixedPoint("depth")] def _opt_control(property_set): return not property_set["depth_fixed_point"] _opt = [Optimize1qGatesDecomposition(basis_gates), CXCancellation()] # 10. Unify all durations (either SI, or convert to dt if known) # Schedule the circuit only when scheduling_method is supplied _time_unit_setup = [ContainsInstruction("delay")] _time_unit_conversion = [TimeUnitConversion(instruction_durations)] def _contains_delay(property_set): return property_set["contains_delay"] _scheduling = [] if scheduling_method: _scheduling += _time_unit_conversion if scheduling_method in {"alap", "as_late_as_possible"}: _scheduling += [ALAPSchedule(instruction_durations)] elif scheduling_method in {"asap", "as_soon_as_possible"}: _scheduling += [ASAPSchedule(instruction_durations)] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # 11. Call measure alignment. Should come after scheduling. if (timing_constraints.granularity != 1 or timing_constraints.min_length != 1 or timing_constraints.acquire_alignment != 1): _alignments = [ ValidatePulseGates(granularity=timing_constraints.granularity, min_length=timing_constraints.min_length), AlignMeasures(alignment=timing_constraints.acquire_alignment), ] else: _alignments = [] # Build pass manager pm1 = PassManager() if coupling_map or initial_layout: pm1.append(_given_layout) pm1.append(_unroll3q) pm1.append(_choose_layout_and_score, condition=_choose_layout_condition) pm1.append(_improve_layout, condition=_not_perfect_yet) pm1.append(_embed) pm1.append(_swap_check) pm1.append(_swap, condition=_swap_condition) pm1.append(_unroll) if (coupling_map and not coupling_map.is_symmetric) or ( target is not None and target.get_non_global_operation_names(strict_direction=True)): pm1.append(_direction_check) pm1.append(_direction, condition=_direction_condition) pm1.append(_reset) pm1.append(_depth_check + _opt + _unroll, do_while=_opt_control) if inst_map and inst_map.has_custom_gate(): pm1.append(PulseGates(inst_map=inst_map)) if scheduling_method: pm1.append(_scheduling) elif instruction_durations: pm1.append(_time_unit_setup) pm1.append(_time_unit_conversion, condition=_contains_delay) pm1.append(_alignments) return pm1
def level_1_pass_manager( pass_manager_config: PassManagerConfig) -> PassManager: """Level 1 pass manager: light optimization by simple adjacent gate collapsing. This pass manager applies the user-given initial layout. If none is given, and a trivial layout (i-th virtual -> i-th physical) makes the circuit fit the coupling map, that is used. Otherwise, the circuit is mapped to the most densely connected coupling subgraph, and swaps are inserted to map. Any unused physical qubit is allocated as ancilla space. The pass manager then unrolls the circuit to the desired basis, and transforms the circuit to match the coupling map. Finally, optimizations in the form of adjacent gate collapse and redundant reset removal are performed. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 1 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or 'dense' routing_method = pass_manager_config.routing_method or 'stochastic' translation_method = pass_manager_config.translation_method or 'translator' scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties # 1. Use trivial layout if no layout given _given_layout = SetLayout(initial_layout) _choose_layout_and_score = [ TrivialLayout(coupling_map), Layout2qDistance(coupling_map, property_name='trivial_layout_score') ] def _choose_layout_condition(property_set): return not property_set['layout'] # 2. Use a better layout on densely connected qubits, if circuit needs swaps if layout_method == 'trivial': _improve_layout = TrivialLayout(coupling_map) elif layout_method == 'dense': _improve_layout = DenseLayout(coupling_map, backend_properties) elif layout_method == 'noise_adaptive': _improve_layout = NoiseAdaptiveLayout(backend_properties) elif layout_method == 'sabre': _improve_layout = SabreLayout(coupling_map, max_iterations=2, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) def _not_perfect_yet(property_set): return property_set['trivial_layout_score'] is not None and \ property_set['trivial_layout_score'] != 0 # 3. Extend dag/layout with ancillas using the full coupling map _embed = [ FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout() ] # 4. Decompose so only 1-qubit and 2-qubit gates remain _unroll3q = Unroll3qOrMore() # 5. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set['is_swap_mapped'] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == 'basic': _swap += [BasicSwap(coupling_map)] elif routing_method == 'stochastic': _swap += [ StochasticSwap(coupling_map, trials=20, seed=seed_transpiler) ] elif routing_method == 'lookahead': _swap += [LookaheadSwap(coupling_map, search_depth=4, search_width=4)] elif routing_method == 'sabre': _swap += [ SabreSwap(coupling_map, heuristic='lookahead', seed=seed_transpiler) ] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 6. Unroll to the basis if translation_method == 'unroller': _unroll = [Unroller(basis_gates)] elif translation_method == 'translator': from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [ UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates) ] elif translation_method == 'synthesis': _unroll = [ Unroll3qOrMore(), Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis(basis_gates), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 7. Fix any bad CX directions _direction_check = [CheckCXDirection(coupling_map)] def _direction_condition(property_set): return not property_set['is_direction_mapped'] _direction = [CXDirection(coupling_map)] # 8. Remove zero-state reset _reset = RemoveResetInZeroState() # 9. Merge 1q rotations and cancel CNOT gates iteratively until no more change in depth _depth_check = [Depth(), FixedPoint('depth')] def _opt_control(property_set): return not property_set['depth_fixed_point'] _opt = [Optimize1qGates(basis_gates), CXCancellation()] # 10. Schedule the circuit only when scheduling_method is supplied if scheduling_method: _scheduling = [TimeUnitAnalysis(instruction_durations)] if scheduling_method in {'alap', 'as_late_as_possible'}: _scheduling += [ALAPSchedule(instruction_durations)] elif scheduling_method in {'asap', 'as_soon_as_possible'}: _scheduling += [ASAPSchedule(instruction_durations)] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # Build pass manager pm1 = PassManager() if coupling_map: pm1.append(_given_layout) pm1.append(_choose_layout_and_score, condition=_choose_layout_condition) pm1.append(_improve_layout, condition=_not_perfect_yet) pm1.append(_embed) pm1.append(_unroll3q) pm1.append(_swap_check) pm1.append(_swap, condition=_swap_condition) pm1.append(_unroll) if coupling_map and not coupling_map.is_symmetric: pm1.append(_direction_check) pm1.append(_direction, condition=_direction_condition) pm1.append(_reset) pm1.append(_depth_check + _opt, do_while=_opt_control) if scheduling_method: pm1.append(_scheduling) return pm1
def test_measure_after_c_if(self): """Test if ALAP/ASAP schedules circuits with c_if after measure with a common clbit. (input) ┌─┐ q_0: ┤M├────────────── └╥┘ ┌───┐ q_1: ─╫────┤ X ├────── ║ └─╥─┘ ┌─┐ q_2: ─╫──────╫─────┤M├ ║ ┌────╨────┐└╥┘ c: 1/═╩═╡ c_0 = T ╞═╩═ 0 └─────────┘ 0 (scheduled - ASAP) ┌─┐┌────────────────┐ q_0: ───────────────────┤M├┤ Delay(200[dt]) ├───────────────────── ┌─────────────────┐└╥┘└─────┬───┬──────┘ q_1: ┤ Delay(1000[dt]) ├─╫───────┤ X ├──────────────────────────── └─────────────────┘ ║ └─╥─┘ ┌─┐┌────────────────┐ q_2: ────────────────────╫─────────╫─────────┤M├┤ Delay(200[dt]) ├ ║ ┌────╨────┐ └╥┘└────────────────┘ c: 1/════════════════════╩════╡ c_0 = T ╞═════╩═══════════════════ 0 └─────────┘ 0 (scheduled - ALAP) ┌─┐┌────────────────┐ q_0: ───────────────────┤M├┤ Delay(200[dt]) ├─── ┌─────────────────┐└╥┘└─────┬───┬──────┘ q_1: ┤ Delay(1000[dt]) ├─╫───────┤ X ├────────── └┬────────────────┤ ║ └─╥─┘ ┌─┐ q_2: ─┤ Delay(200[dt]) ├─╫─────────╫─────────┤M├ └────────────────┘ ║ ┌────╨────┐ └╥┘ c: 1/════════════════════╩════╡ c_0 = T ╞═════╩═ 0 └─────────┘ 0 """ qc = QuantumCircuit(3, 1) qc.measure(0, 0) qc.x(1).c_if(0, 1) qc.measure(2, 0) durations = InstructionDurations([("x", None, 200), ("measure", None, 1000)]) actual_asap = PassManager(ASAPSchedule(durations)).run(qc) actual_alap = PassManager(ALAPSchedule(durations)).run(qc) # start times of 2nd measure depends on ASAP/ALAP expected_asap = QuantumCircuit(3, 1) expected_asap.measure(0, 0) expected_asap.delay(200, 0) expected_asap.delay(1000, 1) expected_asap.x(1).c_if(0, 1) expected_asap.measure(2, 0) expected_asap.delay(200, 2) # delay after measure on q_2 self.assertEqual(expected_asap, actual_asap) expected_aslp = QuantumCircuit(3, 1) expected_aslp.measure(0, 0) expected_aslp.delay(200, 0) expected_aslp.delay(1000, 1) expected_aslp.x(1).c_if(0, 1) expected_aslp.delay(200, 2) expected_aslp.measure(2, 0) # delay before measure on q_2 self.assertEqual(expected_aslp, actual_alap)
def level_0_pass_manager( pass_manager_config: PassManagerConfig) -> PassManager: """Level 0 pass manager: no explicit optimization other than mapping to backend. This pass manager applies the user-given initial layout. If none is given, a trivial layout consisting of mapping the i-th virtual qubit to the i-th physical qubit is used. Any unused physical qubit is allocated as ancilla space. The pass manager then unrolls the circuit to the desired basis, and transforms the circuit to match the coupling map. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 0 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates inst_map = pass_manager_config.inst_map coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or "trivial" routing_method = pass_manager_config.routing_method or "stochastic" translation_method = pass_manager_config.translation_method or "translator" scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties approximation_degree = pass_manager_config.approximation_degree timing_constraints = pass_manager_config.timing_constraints or TimingConstraints( ) unitary_synthesis_method = pass_manager_config.unitary_synthesis_method unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config target = pass_manager_config.target # 1. Decompose so only 1-qubit and 2-qubit gates remain _unroll3q = [ # Use unitary synthesis for basis aware decomposition of UnitaryGates UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, method=unitary_synthesis_method, min_qubits=3, plugin_config=unitary_synthesis_plugin_config, ), Unroll3qOrMore(), ] # 2. Choose an initial layout if not set by user (default: trivial layout) _given_layout = SetLayout(initial_layout) def _choose_layout_condition(property_set): return not property_set["layout"] if layout_method == "trivial": _choose_layout = TrivialLayout(coupling_map) elif layout_method == "dense": _choose_layout = DenseLayout(coupling_map, backend_properties) elif layout_method == "noise_adaptive": _choose_layout = NoiseAdaptiveLayout(backend_properties) elif layout_method == "sabre": _choose_layout = SabreLayout(coupling_map, max_iterations=1, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) # 3. Extend dag/layout with ancillas using the full coupling map _embed = [ FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout() ] # 4. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set["is_swap_mapped"] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == "basic": _swap += [BasicSwap(coupling_map)] elif routing_method == "stochastic": _swap += [ StochasticSwap(coupling_map, trials=20, seed=seed_transpiler) ] elif routing_method == "lookahead": _swap += [LookaheadSwap(coupling_map, search_depth=2, search_width=2)] elif routing_method == "sabre": _swap += [ SabreSwap(coupling_map, heuristic="basic", seed=seed_transpiler) ] elif routing_method == "none": _swap += [ Error( msg= ("No routing method selected, but circuit is not routed to device. " "CheckMap Error: {check_map_msg}"), action="raise", ) ] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 5. Unroll to the basis if translation_method == "unroller": _unroll = [Unroller(basis_gates)] elif translation_method == "translator": from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [ UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, ), UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates, target), ] elif translation_method == "synthesis": _unroll = [ UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, min_qubits=3, plugin_config=unitary_synthesis_plugin_config, ), Unroll3qOrMore(), Collect2qBlocks(), Collect1qRuns(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, ), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 6. Fix any bad CX directions _direction_check = [CheckGateDirection(coupling_map, target)] def _direction_condition(property_set): return not property_set["is_direction_mapped"] _direction = [GateDirection(coupling_map, target)] # 7. Unify all durations (either SI, or convert to dt if known) # Schedule the circuit only when scheduling_method is supplied _time_unit_setup = [ContainsInstruction("delay")] _time_unit_conversion = [TimeUnitConversion(instruction_durations)] def _contains_delay(property_set): return property_set["contains_delay"] _scheduling = [] if scheduling_method: _scheduling += _time_unit_conversion if scheduling_method in {"alap", "as_late_as_possible"}: _scheduling += [ALAPSchedule(instruction_durations)] elif scheduling_method in {"asap", "as_soon_as_possible"}: _scheduling += [ASAPSchedule(instruction_durations)] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # 8. Call measure alignment. Should come after scheduling. if (timing_constraints.granularity != 1 or timing_constraints.min_length != 1 or timing_constraints.acquire_alignment != 1): _alignments = [ ValidatePulseGates(granularity=timing_constraints.granularity, min_length=timing_constraints.min_length), AlignMeasures(alignment=timing_constraints.acquire_alignment), ] else: _alignments = [] # Build pass manager pm0 = PassManager() if coupling_map or initial_layout: pm0.append(_given_layout) pm0.append(_unroll3q) pm0.append(_choose_layout, condition=_choose_layout_condition) pm0.append(_embed) pm0.append(_swap_check) pm0.append(_swap, condition=_swap_condition) pm0.append(_unroll) if (coupling_map and not coupling_map.is_symmetric) or ( target is not None and target.get_non_global_operation_names(strict_direction=True)): pm0.append(_direction_check) pm0.append(_direction, condition=_direction_condition) pm0.append(_unroll) if inst_map and inst_map.has_custom_gate(): pm0.append(PulseGates(inst_map=inst_map)) if scheduling_method: pm0.append(_scheduling) elif instruction_durations: pm0.append(_time_unit_setup) pm0.append(_time_unit_conversion, condition=_contains_delay) pm0.append(_alignments) return pm0
def level_2_pass_manager(pass_manager_config: PassManagerConfig) -> PassManager: """Level 2 pass manager: medium optimization by initial layout selection and gate cancellation using commutativity rules. This pass manager applies the user-given initial layout. If none is given, a search for a perfect layout (i.e. one that satisfies all 2-qubit interactions) is conducted. If no such layout is found, qubits are laid out on the most densely connected subset which also exhibits the best gate fidelities. The pass manager then transforms the circuit to match the coupling constraints. It is then unrolled to the basis, and any flipped cx directions are fixed. Finally, optimizations in the form of commutative gate cancellation and redundant reset removal are performed. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 2 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or "dense" routing_method = pass_manager_config.routing_method or "stochastic" translation_method = pass_manager_config.translation_method or "translator" scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties approximation_degree = pass_manager_config.approximation_degree timing_constraints = pass_manager_config.timing_constraints or TimingConstraints() # 1. Search for a perfect layout, or choose a dense layout, if no layout given _given_layout = SetLayout(initial_layout) def _choose_layout_condition(property_set): # layout hasn't been set yet return not property_set["layout"] # 1a. If layout_method is not set, first try a trivial layout _choose_layout_0 = ( [] if pass_manager_config.layout_method else [ TrivialLayout(coupling_map), Layout2qDistance(coupling_map, property_name="trivial_layout_score"), ] ) # 1b. If a trivial layout wasn't perfect (ie no swaps are needed) then try using # CSP layout to find a perfect layout _choose_layout_1 = ( [] if pass_manager_config.layout_method else CSPLayout(coupling_map, call_limit=1000, time_limit=10, seed=seed_transpiler) ) def _trivial_not_perfect(property_set): # Verify that a trivial layout is perfect. If trivial_layout_score > 0 # the layout is not perfect. The layout is unconditionally set by trivial # layout so we need to clear it before contuing. if property_set["trivial_layout_score"] is not None: if property_set["trivial_layout_score"] != 0: property_set["layout"]._wrapped = None return True return False def _csp_not_found_match(property_set): # If a layout hasn't been set by the time we run csp we need to run layout if property_set["layout"] is None: return True # if CSP layout stopped for any reason other than solution found we need # to run layout since CSP didn't converge. if ( property_set["CSPLayout_stop_reason"] is not None and property_set["CSPLayout_stop_reason"] != "solution found" ): return True return False # 1c. if CSP layout doesn't converge on a solution use layout_method (dense) to get a layout if layout_method == "trivial": _choose_layout_2 = TrivialLayout(coupling_map) elif layout_method == "dense": _choose_layout_2 = DenseLayout(coupling_map, backend_properties) elif layout_method == "noise_adaptive": _choose_layout_2 = NoiseAdaptiveLayout(backend_properties) elif layout_method == "sabre": _choose_layout_2 = SabreLayout(coupling_map, max_iterations=2, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) # 2. Extend dag/layout with ancillas using the full coupling map _embed = [FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout()] # 3. Unroll to 1q or 2q gates _unroll3q = Unroll3qOrMore() # 4. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set["is_swap_mapped"] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == "basic": _swap += [BasicSwap(coupling_map)] elif routing_method == "stochastic": _swap += [StochasticSwap(coupling_map, trials=20, seed=seed_transpiler)] elif routing_method == "lookahead": _swap += [LookaheadSwap(coupling_map, search_depth=5, search_width=5)] elif routing_method == "sabre": _swap += [SabreSwap(coupling_map, heuristic="decay", seed=seed_transpiler)] elif routing_method == "none": _swap += [ Error( msg="No routing method selected, but circuit is not routed to device. " "CheckMap Error: {check_map_msg}", action="raise", ) ] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 5. Unroll to the basis if translation_method == "unroller": _unroll = [Unroller(basis_gates)] elif translation_method == "translator": from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates)] elif translation_method == "synthesis": _unroll = [ Unroll3qOrMore(), Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates), UnitarySynthesis(basis_gates, approximation_degree=approximation_degree), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 6. Fix any bad CX directions _direction_check = [CheckGateDirection(coupling_map)] def _direction_condition(property_set): return not property_set["is_direction_mapped"] _direction = [GateDirection(coupling_map)] # 7. Remove zero-state reset _reset = RemoveResetInZeroState() # 8. 1q rotation merge and commutative cancellation iteratively until no more change in depth _depth_check = [Depth(), FixedPoint("depth")] def _opt_control(property_set): return not property_set["depth_fixed_point"] _opt = [ Optimize1qGatesDecomposition(basis_gates), CommutativeCancellation(basis_gates=basis_gates), ] # 9. Unify all durations (either SI, or convert to dt if known) # Schedule the circuit only when scheduling_method is supplied _scheduling = [TimeUnitConversion(instruction_durations)] if scheduling_method: if scheduling_method in {"alap", "as_late_as_possible"}: _scheduling += [ALAPSchedule(instruction_durations)] elif scheduling_method in {"asap", "as_soon_as_possible"}: _scheduling += [ASAPSchedule(instruction_durations)] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # 10. Call measure alignment. Should come after scheduling. _alignments = [ ValidatePulseGates( granularity=timing_constraints.granularity, min_length=timing_constraints.min_length ), AlignMeasures(alignment=timing_constraints.acquire_alignment), ] # Build pass manager pm2 = PassManager() if coupling_map or initial_layout: pm2.append(_given_layout) pm2.append(_choose_layout_0, condition=_choose_layout_condition) pm2.append(_choose_layout_1, condition=_trivial_not_perfect) pm2.append(_choose_layout_2, condition=_csp_not_found_match) pm2.append(_embed) pm2.append(_unroll3q) pm2.append(_swap_check) pm2.append(_swap, condition=_swap_condition) pm2.append(_unroll) if coupling_map and not coupling_map.is_symmetric: pm2.append(_direction_check) pm2.append(_direction, condition=_direction_condition) pm2.append(_reset) pm2.append(_depth_check + _opt + _unroll, do_while=_opt_control) pm2.append(_scheduling) pm2.append(_alignments) return pm2
def level_2_pass_manager( pass_manager_config: PassManagerConfig) -> PassManager: """Level 2 pass manager: medium optimization by initial layout selection and gate cancellation using commutativity rules. This pass manager applies the user-given initial layout. If none is given, a search for a perfect layout (i.e. one that satisfies all 2-qubit interactions) is conducted. If no such layout is found, qubits are laid out on the most densely connected subset which also exhibits the best gate fidelities. The pass manager then transforms the circuit to match the coupling constraints. It is then unrolled to the basis, and any flipped cx directions are fixed. Finally, optimizations in the form of commutative gate cancellation and redundant reset removal are performed. Note: In simulators where ``coupling_map=None``, only the unrolling and optimization stages are done. Args: pass_manager_config: configuration of the pass manager. Returns: a level 2 pass manager. Raises: TranspilerError: if the passmanager config is invalid. """ basis_gates = pass_manager_config.basis_gates inst_map = pass_manager_config.inst_map coupling_map = pass_manager_config.coupling_map initial_layout = pass_manager_config.initial_layout layout_method = pass_manager_config.layout_method or "dense" routing_method = pass_manager_config.routing_method or "stochastic" translation_method = pass_manager_config.translation_method or "translator" scheduling_method = pass_manager_config.scheduling_method instruction_durations = pass_manager_config.instruction_durations seed_transpiler = pass_manager_config.seed_transpiler backend_properties = pass_manager_config.backend_properties approximation_degree = pass_manager_config.approximation_degree unitary_synthesis_method = pass_manager_config.unitary_synthesis_method timing_constraints = pass_manager_config.timing_constraints or TimingConstraints( ) unitary_synthesis_plugin_config = pass_manager_config.unitary_synthesis_plugin_config target = pass_manager_config.target # 1. Unroll to 1q or 2q gates _unroll3q = [ # Use unitary synthesis for basis aware decomposition of UnitaryGates UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, method=unitary_synthesis_method, min_qubits=3, plugin_config=unitary_synthesis_plugin_config, ), Unroll3qOrMore(), ] # 2. Search for a perfect layout, or choose a dense layout, if no layout given _given_layout = SetLayout(initial_layout) def _choose_layout_condition(property_set): # layout hasn't been set yet return not property_set["layout"] def _vf2_match_not_found(property_set): # If a layout hasn't been set by the time we run vf2 layout we need to # run layout if property_set["layout"] is None: return True # if VF2 layout stopped for any reason other than solution found we need # to run layout since VF2 didn't converge. if (property_set["VF2Layout_stop_reason"] is not None and property_set["VF2Layout_stop_reason"] is not VF2LayoutStopReason.SOLUTION_FOUND): return True return False # 2a. Try using VF2 layout to find a perfect layout _choose_layout_0 = ([] if pass_manager_config.layout_method else VF2Layout( coupling_map, seed=seed_transpiler, call_limit=int(5e6), # Set call limit to ~10 sec with retworkx 0.10.2 time_limit=10.0, properties=backend_properties, )) # 2b. if VF2 layout doesn't converge on a solution use layout_method (dense) to get a layout if layout_method == "trivial": _choose_layout_1 = TrivialLayout(coupling_map) elif layout_method == "dense": _choose_layout_1 = DenseLayout(coupling_map, backend_properties) elif layout_method == "noise_adaptive": _choose_layout_1 = NoiseAdaptiveLayout(backend_properties) elif layout_method == "sabre": _choose_layout_1 = SabreLayout(coupling_map, max_iterations=2, seed=seed_transpiler) else: raise TranspilerError("Invalid layout method %s." % layout_method) # 3. Extend dag/layout with ancillas using the full coupling map _embed = [ FullAncillaAllocation(coupling_map), EnlargeWithAncilla(), ApplyLayout() ] # 4. Swap to fit the coupling map _swap_check = CheckMap(coupling_map) def _swap_condition(property_set): return not property_set["is_swap_mapped"] _swap = [BarrierBeforeFinalMeasurements()] if routing_method == "basic": _swap += [BasicSwap(coupling_map)] elif routing_method == "stochastic": _swap += [ StochasticSwap(coupling_map, trials=20, seed=seed_transpiler) ] elif routing_method == "lookahead": _swap += [LookaheadSwap(coupling_map, search_depth=5, search_width=5)] elif routing_method == "sabre": _swap += [ SabreSwap(coupling_map, heuristic="decay", seed=seed_transpiler) ] elif routing_method == "none": _swap += [ Error( msg= ("No routing method selected, but circuit is not routed to device. " "CheckMap Error: {check_map_msg}"), action="raise", ) ] else: raise TranspilerError("Invalid routing method %s." % routing_method) # 5. Unroll to the basis if translation_method == "unroller": _unroll = [Unroller(basis_gates)] elif translation_method == "translator": from qiskit.circuit.equivalence_library import SessionEquivalenceLibrary as sel _unroll = [ # Use unitary synthesis for basis aware decomposition of UnitaryGates before # custom unrolling UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, ), UnrollCustomDefinitions(sel, basis_gates), BasisTranslator(sel, basis_gates, target), ] elif translation_method == "synthesis": _unroll = [ # Use unitary synthesis for basis aware decomposition of UnitaryGates before # collection UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, min_qubits=3, ), Unroll3qOrMore(), Collect2qBlocks(), ConsolidateBlocks(basis_gates=basis_gates, target=target), UnitarySynthesis( basis_gates, approximation_degree=approximation_degree, coupling_map=coupling_map, backend_props=backend_properties, method=unitary_synthesis_method, plugin_config=unitary_synthesis_plugin_config, ), ] else: raise TranspilerError("Invalid translation method %s." % translation_method) # 6. Fix any bad CX directions _direction_check = [CheckGateDirection(coupling_map, target)] def _direction_condition(property_set): return not property_set["is_direction_mapped"] _direction = [GateDirection(coupling_map, target)] # 7. Remove zero-state reset _reset = RemoveResetInZeroState() # 8. 1q rotation merge and commutative cancellation iteratively until no more change in depth _depth_check = [Depth(), FixedPoint("depth")] def _opt_control(property_set): return not property_set["depth_fixed_point"] _opt = [ Optimize1qGatesDecomposition(basis_gates), CommutativeCancellation(basis_gates=basis_gates), ] # 9. Unify all durations (either SI, or convert to dt if known) # Schedule the circuit only when scheduling_method is supplied _time_unit_setup = [ContainsInstruction("delay")] _time_unit_conversion = [TimeUnitConversion(instruction_durations)] def _contains_delay(property_set): return property_set["contains_delay"] _scheduling = [] if scheduling_method: _scheduling += _time_unit_conversion if scheduling_method in {"alap", "as_late_as_possible"}: _scheduling += [ALAPSchedule(instruction_durations), PadDelay()] elif scheduling_method in {"asap", "as_soon_as_possible"}: _scheduling += [ASAPSchedule(instruction_durations), PadDelay()] else: raise TranspilerError("Invalid scheduling method %s." % scheduling_method) # 10. Call measure alignment. Should come after scheduling. if (timing_constraints.granularity != 1 or timing_constraints.min_length != 1 or timing_constraints.acquire_alignment != 1): _alignments = [ ValidatePulseGates(granularity=timing_constraints.granularity, min_length=timing_constraints.min_length), AlignMeasures(alignment=timing_constraints.acquire_alignment), ] else: _alignments = [] # Build pass manager pm2 = PassManager() if coupling_map or initial_layout: pm2.append(_given_layout) pm2.append(_unroll3q) pm2.append(_choose_layout_0, condition=_choose_layout_condition) pm2.append(_choose_layout_1, condition=_vf2_match_not_found) pm2.append(_embed) pm2.append(_swap_check) pm2.append(_swap, condition=_swap_condition) pm2.append(_unroll) if (coupling_map and not coupling_map.is_symmetric) or ( target is not None and target.get_non_global_operation_names(strict_direction=True)): pm2.append(_direction_check) pm2.append(_direction, condition=_direction_condition) pm2.append(_reset) pm2.append(_depth_check + _opt + _unroll, do_while=_opt_control) if inst_map and inst_map.has_custom_gate(): pm2.append(PulseGates(inst_map=inst_map)) if scheduling_method: pm2.append(_scheduling) elif instruction_durations: pm2.append(_time_unit_setup) pm2.append(_time_unit_conversion, condition=_contains_delay) pm2.append(_alignments) return pm2
def test_insert_dd_ghz_xy4(self): """Test XY4 sequence of DD gates. ┌───┐ ┌───────────────┐ ┌───┐ ┌───────────────┐» q_0: ──────┤ H ├─────────■──┤ Delay(37[dt]) ├──────┤ X ├──────┤ Delay(75[dt]) ├» ┌─────┴───┴─────┐ ┌─┴─┐└───────────────┘┌─────┴───┴─────┐└─────┬───┬─────┘» q_1: ┤ Delay(50[dt]) ├─┤ X ├────────■────────┤ Delay(12[dt]) ├──────┤ X ├──────» ├───────────────┴┐└───┘ ┌─┴─┐ └───────────────┘ └───┘ » q_2: ┤ Delay(750[dt]) ├───────────┤ X ├──────────────■─────────────────────────» ├────────────────┤ └───┘ ┌─┴─┐ » q_3: ┤ Delay(950[dt]) ├────────────────────────────┤ X ├───────────────────────» └────────────────┘ └───┘ » « ┌───┐ ┌───────────────┐ ┌───┐ ┌───────────────┐» «q_0: ──────┤ Y ├──────┤ Delay(76[dt]) ├──────┤ X ├──────┤ Delay(75[dt]) ├» « ┌─────┴───┴─────┐└─────┬───┬─────┘┌─────┴───┴─────┐└─────┬───┬─────┘» «q_1: ┤ Delay(25[dt]) ├──────┤ Y ├──────┤ Delay(26[dt]) ├──────┤ X ├──────» « └───────────────┘ └───┘ └───────────────┘ └───┘ » «q_2: ────────────────────────────────────────────────────────────────────» « » «q_3: ────────────────────────────────────────────────────────────────────» « » « ┌───┐ ┌───────────────┐ «q_0: ──────┤ Y ├──────┤ Delay(37[dt]) ├───────────────── « ┌─────┴───┴─────┐└─────┬───┬─────┘┌───────────────┐ «q_1: ┤ Delay(25[dt]) ├──────┤ Y ├──────┤ Delay(12[dt]) ├ « └───────────────┘ └───┘ └───────────────┘ «q_2: ─────────────────────────────────────────────────── « «q_3: ─────────────────────────────────────────────────── """ dd_sequence = [XGate(), YGate(), XGate(), YGate()] pm = PassManager([ ALAPSchedule(self.durations), DynamicalDecoupling(self.durations, dd_sequence) ]) ghz4_dd = pm.run(self.ghz4) expected = self.ghz4.copy() expected = expected.compose(Delay(50), [1], front=True) expected = expected.compose(Delay(750), [2], front=True) expected = expected.compose(Delay(950), [3], front=True) expected = expected.compose(Delay(37), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(75), [0]) expected = expected.compose(YGate(), [0]) expected = expected.compose(Delay(76), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(75), [0]) expected = expected.compose(YGate(), [0]) expected = expected.compose(Delay(37), [0]) expected = expected.compose(Delay(12), [1]) expected = expected.compose(XGate(), [1]) expected = expected.compose(Delay(25), [1]) expected = expected.compose(YGate(), [1]) expected = expected.compose(Delay(26), [1]) expected = expected.compose(XGate(), [1]) expected = expected.compose(Delay(25), [1]) expected = expected.compose(YGate(), [1]) expected = expected.compose(Delay(12), [1]) self.assertEqual(ghz4_dd, expected)
def test_insert_ghz_uhrig(self): """Test custom spacing (following Uhrig DD [1]). [1] Uhrig, G. "Keeping a quantum bit alive by optimized π-pulse sequences." Physical Review Letters 98.10 (2007): 100504. ┌───┐ ┌──────────────┐ ┌───┐ ┌──────────────┐┌───┐» q_0: ──────┤ H ├─────────■──┤ Delay(3[dt]) ├──────┤ X ├───────┤ Delay(8[dt]) ├┤ X ├» ┌─────┴───┴─────┐ ┌─┴─┐└──────────────┘┌─────┴───┴──────┐└──────────────┘└───┘» q_1: ┤ Delay(50[dt]) ├─┤ X ├───────■────────┤ Delay(300[dt]) ├─────────────────────» ├───────────────┴┐└───┘ ┌─┴─┐ └────────────────┘ » q_2: ┤ Delay(750[dt]) ├──────────┤ X ├──────────────■──────────────────────────────» ├────────────────┤ └───┘ ┌─┴─┐ » q_3: ┤ Delay(950[dt]) ├───────────────────────────┤ X ├────────────────────────────» └────────────────┘ └───┘ » « ┌───────────────┐┌───┐┌───────────────┐┌───┐┌───────────────┐┌───┐┌───────────────┐» «q_0: ┤ Delay(13[dt]) ├┤ X ├┤ Delay(16[dt]) ├┤ X ├┤ Delay(20[dt]) ├┤ X ├┤ Delay(16[dt]) ├» « └───────────────┘└───┘└───────────────┘└───┘└───────────────┘└───┘└───────────────┘» «q_1: ───────────────────────────────────────────────────────────────────────────────────» « » «q_2: ───────────────────────────────────────────────────────────────────────────────────» « » «q_3: ───────────────────────────────────────────────────────────────────────────────────» « » « ┌───┐┌───────────────┐┌───┐┌──────────────┐┌───┐┌──────────────┐ «q_0: ┤ X ├┤ Delay(13[dt]) ├┤ X ├┤ Delay(8[dt]) ├┤ X ├┤ Delay(3[dt]) ├ « └───┘└───────────────┘└───┘└──────────────┘└───┘└──────────────┘ «q_1: ──────────────────────────────────────────────────────────────── « «q_2: ──────────────────────────────────────────────────────────────── « «q_3: ──────────────────────────────────────────────────────────────── « """ n = 8 dd_sequence = [XGate()] * n # uhrig specifies the location of the k'th pulse def uhrig(k): return np.sin(np.pi * (k + 1) / (2 * n + 2))**2 # convert that to spacing between pulses (whatever finite duration pulses have) spacing = [] for k in range(n): spacing.append(uhrig(k) - sum(spacing)) spacing.append(1 - sum(spacing)) pm = PassManager([ ALAPSchedule(self.durations), DynamicalDecoupling(self.durations, dd_sequence, qubits=[0], spacing=spacing), ]) ghz4_dd = pm.run(self.ghz4) expected = self.ghz4.copy() expected = expected.compose(Delay(50), [1], front=True) expected = expected.compose(Delay(750), [2], front=True) expected = expected.compose(Delay(950), [3], front=True) expected = expected.compose(Delay(3), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(8), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(13), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(16), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(20), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(16), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(13), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(8), [0]) expected = expected.compose(XGate(), [0]) expected = expected.compose(Delay(3), [0]) expected = expected.compose(Delay(300), [1]) self.assertEqual(ghz4_dd, expected)