def check(m: Module, data: Snapshot, alu: Signal):
m.d.comb += [
Assert(data.read_data[0].matches(MUL.opcode)),
]
for i in range(1, 10):
m.d.comb += [
Assert(Past(alu.oper, i) == Operation.MUL),
]
for i in range(3, 10):
m.d.comb += [
Assert(Past(alu.inputa, i) == data.pre.Y),
Assert(Past(alu.inputb, i) == data.pre.A),
]
m.d.comb += [
Assert(data.post.A == Past(alu.result, 1)),
Assert(data.post.X == data.pre.X),
Assert(data.post.Y == Past(alu.result, 2)),
Assert(data.post.SP == data.pre.SP),
Assert(data.post.PC == add16(data.pre.PC, 1)),
]
m.d.comb += [
Assert(data.addresses_read == 1),
Assert(data.addresses_written == 0),
Assert(data.read_addr[0] == add16(data.pre.PC, 0)),
]
def check(m: Module, data: Snapshot, alu: Signal):
m.d.comb += [
Assert(data.read_data[0].matches(MOV_A_read.opcode)),
]
m.d.comb += [
Assert(Past(alu.oper, 4) == Operation.NOP),
Assert(Past(alu.oper, 3) == Operation.NOP),
Assert(Past(alu.oper, 2) == Operation.NOP),
Assert(Past(alu.oper, 1) == Operation.OOR),
Assert(Past(alu.inputa) == data.read_data[3]),
Assert(Past(alu.inputb) == 0),
Assert(Past(alu.result) == data.read_data[3]),
]
m.d.comb += [
Assert(data.post.A == Past(alu.result)),
Assert(data.post.X == data.pre.X),
Assert(data.post.Y == data.pre.Y),
Assert(data.post.SP == data.pre.SP),
Assert(data.post.PC == add16(data.pre.PC, 3)),
]
m.d.comb += [
Assert(data.addresses_read == 4),
Assert(data.addresses_written == 0),
Assert(data.read_addr[0] == add16(data.pre.PC, 0)),
Assert(data.read_addr[1] == add16(data.pre.PC, 1)),
Assert(data.read_addr[2] == add16(data.pre.PC, 2)),
Assert(data.read_addr[3] == Cat(data.read_data[1], data.read_data[2])),
]
def check(m: Module, data: Snapshot, alu: Signal):
m.d.comb += [
Assert(data.read_data[0].matches(JMP.opcode)),
]
m.d.comb += [
Assert(Past(alu.oper, 3) == Operation.NOP),
Assert(Past(alu.oper, 2) == Operation.NOP),
Assert(Past(alu.oper, 1) == Operation.NOP),
]
m.d.comb += [
Assert(data.post.A == data.pre.A),
Assert(data.post.X == data.pre.X),
Assert(data.post.Y == data.pre.Y),
Assert(data.post.SP == data.pre.SP),
Assert(data.post.PC[:8] == data.read_data[1]),
Assert(data.post.PC[8:] == data.read_data[2]),
Assert(data.post.PSW == data.pre.PSW),
]
m.d.comb += [
Assert(data.addresses_read == 3),
Assert(data.addresses_written == 0),
Assert(data.read_addr[0] == add16(data.pre.PC, 0)),
Assert(data.read_addr[1] == add16(data.pre.PC, 1)),
Assert(data.read_addr[2] == add16(data.pre.PC, 2)),
]
def synth(core, m: Module):
with m.If(core.cycle == 1):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(2),
]
with m.If(core.cycle == 2):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.tmp.eq(core.dout),
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(3),
]
with m.If(core.cycle == 3):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(Cat(core.tmp, core.dout)),
core.enable.eq(1),
core.addr.eq(Cat(core.tmp, core.dout)),
core.RWB.eq(1),
core.cycle.eq(1),
]
def elaborate(self, platform: Platform) -> Module:
m = Module()
m.submodules.alu = self.alu = ALU()
"""Fetch the opcode, common for all instr"""
m.d.sync += self.opcode.eq(Mux(self.cycle == 1, self.dout, self.opcode))
with m.Switch(Mux(self.cycle == 1, self.dout, self.opcode)):
for i in implemented.implemented:
with m.Case(i.opcode):
i.synth(self, m)
with m.Default():
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(1),
]
if self.verification is not None:
self.verify(m)
with m.If(Initial()):
m.d.sync += [
self.reg.A.eq(AnyConst(8)),
self.reg.X.eq(AnyConst(8)),
self.reg.Y.eq(AnyConst(8)),
self.reg.SP.eq(AnyConst(16)),
self.reg.PC.eq(AnyConst(16)),
]
m.d.sync += [
self.reg.PSW.N.eq(AnyConst(1)),
self.reg.PSW.V.eq(AnyConst(1)),
self.reg.PSW.P.eq(AnyConst(1)),
self.reg.PSW.B.eq(AnyConst(1)),
self.reg.PSW.H.eq(AnyConst(1)),
self.reg.PSW.I.eq(AnyConst(1)),
self.reg.PSW.Z.eq(AnyConst(1)),
self.reg.PSW.C.eq(AnyConst(1)),
]
return m
def synth(core, m: Module):
for i in range(1, 11):
with m.If(core.cycle == i):
m.d.comb += [
core.alu.inputa.eq(core.reg.Y),
core.alu.inputb.eq(core.reg.A),
core.alu.oper.eq(Operation.DIV),
]
m.d.sync += [
core.reg.PC.eq(core.reg.PC),
core.enable.eq(0),
core.addr.eq(core.reg.PC),
core.RWB.eq(1),
core.cycle.eq(i + 1),
]
with m.If(core.cycle == 11):
m.d.comb += [
core.alu.oper.eq(Operation.DIV),
]
m.d.sync += [
core.reg.Y.eq(core.alu.result),
core.enable.eq(0),
core.reg.PC.eq(core.reg.PC),
core.addr.eq(core.reg.PC),
core.RWB.eq(1),
core.cycle.eq(12),
]
with m.If(core.cycle == 12):
m.d.comb += [
core.alu.oper.eq(Operation.DIV),
]
m.d.sync += [
core.reg.A.eq(core.alu.result),
core.enable.eq(1),
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(1),
]
def synth(core, m: Module):
with m.If(core.cycle == 1):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(2),
]
with m.If(core.cycle == 2):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.tmp.eq(core.dout),
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(3),
]
with m.If(core.cycle == 3):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(core.reg.PC),
core.enable.eq(1),
core.addr.eq(Cat(core.tmp, core.dout)),
core.RWB.eq(1),
core.cycle.eq(4),
]
with m.If(core.cycle == 4):
m.d.comb += [
core.alu.inputa.eq(core.dout),
core.alu.inputb.eq(Const(0x00)),
core.alu.oper.eq(Operation.OOR),
]
m.d.sync += [
core.reg.A.eq(core.alu.result),
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(1),
]