def initExp(self):
print('******************************************************************************************************************************************************************')
print('initializing experiment')
self.mod_disable()
reset()
dds_lock_pll.dds_lock_pll()
self.mod_enable()
self.mod_report()
def __init__(self): self.dacRes = 65535 #0xffff self.dacRange = [-10, 10] self.dacIncrMax = 0xffffffff # 32bit self.dacRampTimeRes = 2000 #20us in the unit of system clk (10ns) self.ddsAmpRange = [0, 5] self.ddsFreqRange = [0, 500] self.accUpdateFreq = 1.0 # accumulator update freq in MHz, not really used, for reminder self.ddsUpdateFreq = 50.0 # dds update freq in kHz, not really used, for reminder self.ddsFreqRangeConv = 0xffffffff / 500.0 #8589930 # (2^32 - 1)/500 MHz self.ddsAmpRangeConv = 0x3ff/100 # (2^10 - 1)/100 self.ddsFreqIncMax = 0xfffffffffff # 32 ftw + 12 acc = 44bit self.ddsAmpIncMax = 0x3fffff # 10 atw + 12 acc = 22bit # self.ddsTimeRes = 1.0e3 # in us # initialize DACs self.dac0 = DAC81416(fifo_devices['DAC81416_0']) self.dac1 = DAC81416(fifo_devices['DAC81416_1']) self.dds0 = AD9959(fifo_devices['AD9959_0']) self.dds1 = AD9959(fifo_devices['AD9959_1']) self.dds2 = AD9959(fifo_devices['AD9959_2']) self.fifo_dac0_seq = AXIS_FIFO(fifo_devices['DAC81416_0_seq']) self.fifo_dac1_seq = AXIS_FIFO(fifo_devices['DAC81416_1_seq']) dds_lock_pll.dds_lock_pll() # initialize DDSs self.fifo_dds0_atw_seq = AXIS_FIFO(fifo_devices['AD9959_0_seq_atw']) self.fifo_dds0_ftw_seq = AXIS_FIFO(fifo_devices['AD9959_0_seq_ftw']) self.fifo_dds1_atw_seq = AXIS_FIFO(fifo_devices['AD9959_1_seq_atw']) self.fifo_dds1_ftw_seq = AXIS_FIFO(fifo_devices['AD9959_1_seq_ftw']) self.fifo_dds2_atw_seq = AXIS_FIFO(fifo_devices['AD9959_2_seq_atw']) self.fifo_dds2_ftw_seq = AXIS_FIFO(fifo_devices['AD9959_2_seq_ftw']) # self.dds = AD9959(dds_device) # initialize DDS self.gpio2 = AXI_GPIO(gpio_devices['axi_gpio_2']) self.fifo_dio_seq = AXIS_FIFO(fifo_devices['GPIO_seq']) reset()
ddsConv = self.ddsAmpRangeConv
start = int(float(snapshot_split[3].strip('s')) * ddsConv)
end = int(float(snapshot_split[4].strip('e')) * ddsConv)
duration = int(snapshot_split[5].strip('d').strip('\0'), 16)
return [t, chan, aorf, start, end, duration]
if __name__ == "__main__":
from soft_trigger import trigger
from reset_all import reset
import dds_lock_pll
byte_buf_dio = 't0000A000_bF000000100000001\0t0000A3E8_b0000000000000000\0t0000A7D0_b0000000000000001\0'
byte_buf0 = 't00000064_c0000_a_s000.500_e000.000_d00000000\0'
byte_buf1 = 't00000064_c0000_f_s080.000_e000.000_d00000000\0'
byte_buf_dac = 't00000064_c0000_s00.000_e01.000_d0007A120'
seq = sequencer()
seq.mod_disable()
reset()
dds_lock_pll.dds_lock_pll()
# seq.dds_seq_write_points(47, byte_buf0, 1)
# seq.dds_seq_write_points(47, byte_buf1, 1)
# seq.dds_seq_write_atw_points()
seq.dds_seq_write_ftw_points()
# seq.set_DAC(0, 1)
# seq.dac_seq_write_points(42, byte_buf_dac, 1)
seq.dio_seq_write_points(28, byte_buf_dio, 3)
seq.mod_enable()
trigger()
tester.dac_seq_write_points()
tester.dio_seq_write_points()
# ~ print('Next, we need to enable modulation')
# ~ print(' tester.mod_enable()')
# ~ print('Now, we can use the software trigger')
# ~ print(' trigger()')
# ~ print('All AXI peripherals can be reset, note this does not disable modulation')
# ~ print(' reset()')
# ~ print('Finally, don\'t forget to disable modulation again')
# ~ print(' tester.mod_disable()')
if __name__ == "__main__":
tester = DAC_ramp_tester(fifo_devices['DAC81416_0'],
fifo_devices['DAC81416_1'],
fifo_devices['DAC81416_0_seq'],
fifo_devices['DAC81416_1_seq'],
fifo_devices['GPIO_seq'])
reset_all.reset()
# sleep(1)
program(tester)
# sleep(1)
tester.mod_enable()
# sleep(1)
soft_trigger.trigger()
sleep(5)
#reset_all.reset()
tester.mod_disable()
def initExp(self):
print '******************************************************************************************************************************************************************'
print 'initializing experiment'
self.mod_disable()
reset()
dds_lock_pll.dds_lock_pll()
