def serio_ex(clock, reset, sdi, sdo, Np=8): pin = [Signal(intbv(0)[8:]) for _ in range(Np)] pout = [Signal(intbv(0)[8:]) for _ in range(Np)] io_inst = io_stub(clock, reset, sdi, sdo, pin, pout) @always_seq(clock.posedge, reset=reset) def beh(): for ii in range(Np): pout[ii].next = pin[ii] return myhdl.instances()
def _test(): tbclk = clock.gen() tbdut = io_stub(clock, reset, sdi, sdo, pin, pout) @instance def tbstim(): yield reset.pulse(13) yield clock.posedge # @todo: actually test something for ii in range(1000): yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim
def _bench_serio(): tbclk = clock.gen() tbdut = io_stub(clock, reset, sdi, sdo, pin, pout) @instance def tbstim(): yield reset.pulse(13) yield clock.posedge # @todo: actually test something for ii in range(1000): yield clock.posedge raise StopSimulation return tbdut, tbclk, tbstim
def bench_serio(): tbclk = clock.gen() tbdut = io_stub(clock, reset, sdi, sdo, pin, pout, valid) @instance def tbstim(): yield reset.pulse(13) yield clock.posedge for pp in pout: pp.next = 0 sdi.next = False yield delay(200) yield clock.posedge for ii in range(1000): yield clock.posedge assert not sdo assert pin[0] == 0 for pp in pout: pp.next = 0xFFFF sdi.next = True yield valid.posedge yield delay(200) yield clock.posedge for ii in range(1000): yield clock.posedge assert sdo assert pin[0] == 0xFFFF raise StopSimulation return tbdut, tbclk, tbstim
def bench_serio(): tbclk = clock.gen() tbdut = io_stub(clock, reset, sdi, sdo, pin, pout, valid) @instance def tbstim(): yield reset.pulse(13) yield clock.posedge for pp in pout: pp.next = 0 sdi.next = False yield delay(200) yield clock.posedge for ii in range(1000): yield clock.posedge assert sdo == False assert pin[0] == 0 for pp in pout: pp.next = 0xFFFF sdi.next = True yield valid.posedge yield delay(200) yield clock.posedge for ii in range(1000): yield clock.posedge assert sdo == True assert pin[0] == 0xFFFF raise StopSimulation return tbdut, tbclk, tbstim
def top_stub(clock, reset, sdi, sdo): pin = [Signal(intbv(0)[16:0]) for _ in range(1)] pout = [Signal(intbv(0)[16:0]) for _ in range(3)] valid = Signal(bool(0)) stub_inst = io_stub(clock, reset, sdi, sdo, pin, pout, valid) return stub_inst