예제 #1
0
    def bench():
        tbdut = xula_vga(
            clock,
            reset,
            vselect,
            vga_hsync,
            vga_vsync,
            vga_red,
            vga_green,
            vga_blue,
            pxlen,
            active,
            resolution=resolution,
            color_depth=color_depth,
            refresh_rate=refresh_rate,
            line_rate=line_rate,
        )
        tbclk = clock.gen()

        mdl = VGADisplay(
            frequency=clock.frequency,
            resolution=resolution,
            refresh_rate=refresh_rate,
            line_rate=line_rate,
            color_depth=color_depth,
        )
        tbmdl = mdl.process(glbl, vga)

        @instance
        def tbstim():
            yield delay(100000)
            raise StopSimulation

        return tbdut, tbclk, tbmdl, tbstim
예제 #2
0
    def bench():
        tbdut = zybo_vga(led,
                         btn,
                         vga_red,
                         vga_green,
                         vga_blue,
                         vga_hsync,
                         vga_vsync,
                         clock,
                         resolution=resolution,
                         color_depth=color_depth,
                         refresh_rate=refresh_rate,
                         line_rate=line_rate)
        tbclk = clock.gen()
        mdl = VGADisplay(frequency=clock.frequency,
                         resolution=resolution,
                         refresh_rate=refresh_rate,
                         line_rate=line_rate,
                         color_depth=color_depth)
        tbmdl = mdl.process(glbl, vga)

        @instance
        def tbstim():
            yield delay(100000)
            raise StopSimulation

        return tbdut, tbclk, tbmdl, tbstim
예제 #3
0
    def _bench_vgasys():
        # top-level VGA system
        tbdut = mm_vgasys(clock,
                          reset,
                          vselect,
                          vga.hsync,
                          vga.vsync,
                          vga.red,
                          vga.green,
                          vga.blue,
                          vga.pxlen,
                          vga.active,
                          resolution=resolution,
                          color_depth=color_depth,
                          refresh_rate=refresh_rate,
                          line_rate=line_rate)

        # group global signals
        glbl = Global(clock=clock, reset=reset)

        # a display for each dut
        mvd = VGADisplay(frequency=clock.frequency,
                         resolution=resolution,
                         refresh_rate=refresh_rate,
                         line_rate=line_rate,
                         color_depth=color_depth)

        # connect VideoDisplay model to the VGA signals
        tbvd = mvd.process(glbl, vga)
        # clock generator
        tbclk = clock.gen()

        @instance
        def tbstim():
            reset.next = reset.active
            yield delay(18)
            reset.next = not reset.active

            # Wait till a full screen has been updated
            while mvd.update_cnt < 3:
                yield delay(1000)

            print("display updates complete")
            time.sleep(1)
            # @todo: verify video system memory is correct!
            # @todo: (self checking!).  Read one of the frame
            # @todo: png's and verify a couple bars are expected

            raise StopSimulation

        return tbclk, tbvd, tbstim, tbdut
예제 #4
0
파일: test_vgasys.py 프로젝트: FelixVi/rhea
    def bench_vgasys():
        # top-level VGA system 
        tbdut = mm_vgasys(
            clock, reset, vselect, vga.hsync, vga.vsync,
            vga.red, vga.green, vga.blue, vga.pxlen, vga.active,
            resolution=resolution,
            color_depth=color_depth,
            refresh_rate=refresh_rate,
            line_rate=line_rate
        )

        # group global signals
        glbl = Global(clock=clock, reset=reset)

        # a display for each dut        
        mvd = VGADisplay(
            frequency=clock.frequency,
            resolution=resolution,
            refresh_rate=refresh_rate,
            line_rate=line_rate,
            color_depth=color_depth
        )

        # connect VideoDisplay model to the VGA signals
        tbvd = mvd.process(glbl, vga)
        # clock generator
        tbclk = clock.gen()

        @instance
        def tbstim():
            reset.next = reset.active
            yield delay(18)
            reset.next = not reset.active
            
            # Wait till a full screen has been updated
            while mvd.update_cnt < 3:
                 yield delay(1000)

            print("display updates complete")
            time.sleep(1)
            # @todo: verify video system memory is correct!
            # @todo: (self checking!).  Read one of the frame
            # @todo: png's and verify a couple bars are expected

            raise StopSimulation

        return tbclk, tbvd, tbstim, tbdut