def test_known_prbs7(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# computed by hand
expected_pattern = (0x3F, 0x10, 0x0C, 0xC5, 0x13, 0xCD, 0x95, 0x2F)
@myhdl.block
def bench_prbs7():
tbdut = prbs_generate(glbl, prbs, order=7, initval=0x7F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# there is one zero at the beginning
yield clock.posedge
for ii, ep in enumerate(expected_pattern):
yield clock.posedge
assert prbs == ep
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_prbs7, timescale='1ps', args=args)
def test_known_prbs7(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# computed by hand
expected_pattern = (0x3F, 0x10, 0x0C, 0xC5, 0x13, 0xCD, 0x95, 0x2F)
def _bench_prbs7():
tbdut = prbs_generate(glbl, prbs, order=7, initval=0x7F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# there is one zero at the beginning
yield clock.posedge
for ii, ep in enumerate(expected_pattern):
yield clock.posedge
assert prbs == ep
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_prbs7, timescale='1ps', args=args)
def test_prbs_word_lengths(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
@myhdl.block
def bench_prbs():
# currently only order 7, 9, 11, 15, 23, and 31 are coded in
# prbs feedback tap table, limit testing to one of these patterns
tbdut = prbs_generate(glbl, prbs, order=23)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# this test doesn't check the output (bad) simply checks that
# the module doesn't choke on the various word-lengths
for ii in range(27):
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
for wl in [2**ii for ii in range(11)]:
prbs = Signal(intbv(0)[wl:])
run_testbench(bench_prbs, timescale='1ps', args=args)
def test_spi_cso_config(args=None):
args = tb_default_args()
# get an instance of the control-status object
cso = spi_controller.cso()
assert isinstance(cso, spi.cso.ControlStatus)
# set a default configuration
cso.loopback.initial_value = False
cso.clock_polarity.initial_value = True
cso.clock_phase.initial_value = True
cso.clock_divisor.initial_value = 2
cso.slave_select.initial_value = 0x10
cso.isstatic = True
def bench():
tbdut = cso.get_generators()
@instance
def tbstim():
yield delay(10)
assert not cso.loopback
assert cso.clock_polarity
assert cso.clock_phase
assert cso.clock_divisor == 2
assert cso.slave_select == 0x10
yield delay(10)
raise StopSimulation
return tbdut, tbstim
run_testbench(bench, args)
def test_spi_models(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
glbl = Global(clock)
ibus = Barebone(glbl)
spibus = SPIBus()
def bench():
tbdut = spi_controller_model(clock, ibus, spibus)
tbspi = SPISlave().process(spibus)
tbclk = clock.gen()
@instance
def tbstim():
yield clock.posedge
yield ibus.writetrans(0x00, 0xBE)
yield delay(100)
yield ibus.readtrans(0x00)
raise StopSimulation
return tbdut, tbspi, tbclk, tbstim
run_testbench(bench, args=args)
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog.no_testbench = True
myhdl.toVHDL.directory = 'output'
# convert the generator
myhdl.toVerilog(prbs_generate, glbl, prbs, order=23)
myhdl.toVHDL(prbs_generate, glbl, prbs, order=23)
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
myhdl.toVerilog(prbs_check,
glbl,
prbs,
locked,
word_count,
error_count,
order=23)
myhdl.toVHDL(prbs_check,
glbl,
prbs,
locked,
word_count,
error_count,
order=23)
def testbench_memmap(args=None):
""" """
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
csbus = Barebone(glbl, data_width=8, address_width=16)
@myhdl.block
def bench_memmap():
tbdut = peripheral(csbus)
tbclk = clock.gen()
print(csbus.regfiles)
@instance
def tbstim():
yield reset.pulse(111)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_memmap)
def test_prbs_word_lengths(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
def _bench_prbs():
# currently only order 7, 9, 11, 15, 23, and 31 are coded in
# prbs feedback tap table, limit testing to one of these patterns
tbdut = prbs_generate(glbl, prbs, order=23)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# this test doesn't check the output (bad) simply checks that
# the module doesn't choke on the various word-lengths
for ii in range(27):
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
for wl in [2**ii for ii in range(11)]:
prbs = Signal(intbv(0)[wl:])
run_testbench(_bench_prbs, timescale='1ps', args=args)
def test_spi_slave(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
spibus = SPIBus()
fifobus = FIFOBus()
def bench_spi_slave():
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(40)
yield clock.posedge
yield spibus.writeread(0x55)
yield spibus.writeread(0xAA)
assert spibus.get_read_data() == 0x55
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_spi_slave, args=args)
def test_known_prbs5(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
expected_pattern = (0xC7, 0xAE, 0x90, 0xE6,)
@myhdl.block
def bench_prbs5():
tbdut = prbs_generate(glbl, prbs, order=5, initval=0x1F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
for ii, ep in enumerate(expected_pattern):
assert prbs == ep
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_prbs5, timescale='1ps', args=args)
def testbench_memmap(args=None):
""" """
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
csbus = Barebone(glbl, data_width=8, address_width=16)
@myhdl.block
def bench_memmap():
tbdut = peripheral(csbus)
tbclk = clock.gen()
print(csbus.regfiles)
@instance
def tbstim():
yield reset.pulse(111)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_memmap)
def testbench_streamer(args=None):
args = tb_default_args(args)
if not hasattr(args, 'keep'):
args.keep = False
if not hasattr(args, 'bustype'):
args.bustype = 'barebone'
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
def _bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(_bench_streamer, args=args)
myhdl.toVerilog.name = "{}".format(streamer_top.__name__)
if args.keep:
myhdl.toVerilog.name += '_keep'
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(streamer_top, clock, reset, upstream, downstream)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
glbl = Global(clock, None)
led = Signal(intbv(0)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_rts = Signal(bool(0))
uartmdl = UARTModel()
@myhdl.block
def bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = icestick_blinky_host(clock, led, pmod,
uart_tx, uart_rx,
uart_dtr, uart_rts)
@instance
def tbstim():
yield delay(1000)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = int((1/115200.) / 1e-9) * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(bench_ibh, args=args)
inst = icestick_blinky_host(
clock, led, pmod,
uart_tx, uart_rx, uart_dtr, uart_rts
)
tb_convert(inst)
def test_elink_interfaces(args=None):
""" test the ELink interface """
args = tb_default_args(args)
clock = Signal(bool(0))
# create the interfaces
elink = ELink() # links the two components (models)
emesh = EMesh(clock) # interface into the Elink external component
@myhdl.block
def bench_elink_interface():
tbnorth = elink_external_model(elink, emesh)
tbsouth = elink_asic_model(elink)
@always(delay(2500))
def tbclk():
clock.next = not clock
@instance
def tbstim():
yield delay(1111)
yield clock.posedge
# send a bunch of write packets
print("send packets")
save_data = []
yield emesh.write(0xDEEDA5A5, 0xDECAFBAD, 0xC0FFEE)
save_data.append(0xDECAFBAD)
for ii in range(10):
addr = randint(0, 1024)
data = randint(0, (2**32)-1)
save_data.append(data)
yield emesh.write(addr, data, ii)
# the other device is a simple loopback, should receive
# the same packets sent.
while emesh.txwr_fifo.count > 0:
print(" waiting ... {}".format(emesh))
yield delay(8000)
print("get packets looped back, ")
while len(save_data) > 0:
yield delay(8000)
pkt = emesh.get_packet('wr')
if pkt is not None:
assert pkt.data == save_data[0], \
"{} ... {:08X} != {:08X}".format(
pkt, int(pkt.data), save_data[0])
save_data.pop(0)
for ii in range(27):
yield clock.posedge
raise StopSimulation
return tbclk, tbnorth, tbsouth, tbstim
run_testbench(bench_elink_interface, timescale='1ps', args=args)
def test_elink_interfaces(args=None):
""" test the ELink interface """
args = tb_default_args(args)
clock = Signal(bool(0))
# create the interfaces
elink = ELink() # links the two components (models)
emesh = EMesh(clock) # interface into the Elink external component
@myhdl.block
def bench_elink_interface():
tbnorth = elink_external_model(elink, emesh)
tbsouth = elink_asic_model(elink)
@always(delay(2500))
def tbclk():
clock.next = not clock
@instance
def tbstim():
yield delay(1111)
yield clock.posedge
# send a bunch of write packets
print("send packets")
save_data = []
yield emesh.write(0xDEEDA5A5, 0xDECAFBAD, 0xC0FFEE)
save_data.append(0xDECAFBAD)
for ii in range(10):
addr = randint(0, 1024)
data = randint(0, (2**32) - 1)
save_data.append(data)
yield emesh.write(addr, data, ii)
# the other device is a simple loopback, should receive
# the same packets sent.
while emesh.txwr_fifo.count > 0:
print(" waiting ... {}".format(emesh))
yield delay(8000)
print("get packets looped back, ")
while len(save_data) > 0:
yield delay(8000)
pkt = emesh.get_packet('wr')
if pkt is not None:
assert pkt.data == save_data[0], \
"{} ... {:08X} != {:08X}".format(
pkt, int(pkt.data), save_data[0])
save_data.pop(0)
for ii in range(27):
yield clock.posedge
raise StopSimulation
return tbclk, tbnorth, tbsouth, tbstim
run_testbench(bench_elink_interface, timescale='1ps', args=args)
def testbench_streamer(args=None):
args = tb_default_args(args)
if not hasattr(args, 'keep'):
args.keep = False
if not hasattr(args, 'bustype'):
args.bustype = 'barebone'
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
@myhdl.block
def bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(bench_streamer, args=args)
inst = streamer_top(clock, reset, upstream, downstream)
tb_convert(inst)
def testbench_streamer(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
def _bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(_bench_streamer, args=args)
myhdl.toVerilog.name = "{}".format(streamer_top.__name__)
if args.keep:
myhdl.toVerilog.name += '_keep'
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(streamer_top, clock, reset, upstream, downstream)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
glbl = Global(clock, None)
led = Signal(intbv(0)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_rts = Signal(bool(0))
uartmdl = UARTModel()
def _bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = icestick_blinky_host(clock, led, pmod,
uart_tx, uart_rx,
uart_dtr, uart_rts)
@instance
def tbstim():
yield delay(1000)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = int((1/115200.) / 1e-9) * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(_bench_ibh, args=args)
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(icestick_blinky_host, clock, led, pmod,
uart_tx, uart_rx, uart_dtr, uart_rts)
def test_spi_slave(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
spibus, fifobus = SPIBus(), FIFOBus()
# monitor the FIFOBus signals
data = Signal(intbv(0)[8:])
rd, wr, full, empty = Signals(bool(0), 4)
@myhdl.block
def bench_spi_slave():
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(40)
yield delay(1000)
yield clock.posedge
# @todo: make generic
# @todo: random_sequence = [randint(0, fifobus.write_data.max) for _ in range(ntx)]
yield spibus.writeread(0x55)
yield spibus.writeread(0xAA)
yield spibus.writeread(0xCE)
assert spibus.get_read_data() == 0x55
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xAA
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xCE
raise StopSimulation
@always_comb
def tb_fifo_loopback():
if not fifobus.full:
fifobus.write.next = not fifobus.empty
fifobus.read.next = not fifobus.empty
fifobus.write_data.next = fifobus.read_data
# monitors
@always_comb
def tbmon():
data.next = fifobus.read_data
rd.next = fifobus.read
wr.next = fifobus.write
full.next = fifobus.full
empty.next = fifobus.empty
return tbdut, tbclk, tbstim, tb_fifo_loopback, tbmon
run_testbench(bench_spi_slave, args=args)
def test_memmap_command_bridge(args=None):
nloops = 37
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
fbtx, fbrx = FIFOBus(), FIFOBus()
memmap = Barebone(glbl, data_width=32, address_width=28)
fbtx.clock = clock
fbrx.clock = clock
def _bench_command_bridge():
tbclk = clock.gen()
tbdut = memmap_command_bridge(glbl, fbtx, fbrx, memmap)
tbfii = fifo_fast(clock, reset, fbtx)
tbfio = fifo_fast(clock, reset, fbrx)
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20)-1)
randdata = randint(0, (2**32)-1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
run_testbench(_bench_command_bridge, args=args)
def test_memmap_command_bridge(args=None):
nloops = 37
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
fbtx, fbrx = FIFOBus(), FIFOBus()
memmap = Barebone(glbl, data_width=32, address_width=28)
fbtx.clock = clock
fbrx.clock = clock
def _bench_command_bridge():
tbclk = clock.gen()
tbdut = memmap_command_bridge(glbl, fbtx, fbrx, memmap)
tbfii = fifo_fast(clock, reset, fbtx)
tbfio = fifo_fast(clock, reset, fbrx)
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20) - 1)
randdata = randint(0, (2**32) - 1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(fbtx)
yield pkt.get(fbrx, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
return tbclk, tbdut, tbfii, tbfio, tbmem, tbstim
run_testbench(_bench_command_bridge, args=args)
def test_spi_slave(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
spibus, fifobus = SPIBus(), FIFOBus()
# monitor the FIFOBus signals
data = Signal(intbv(0)[8:])
rd, wr, full, empty = Signals(bool(0), 4)
@myhdl.block
def bench_spi_slave():
tbdut = spi_slave_fifo(glbl, spibus, fifobus)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(40)
yield delay(1000)
yield clock.posedge
# @todo: make generic
# @todo: random_sequence = [randint(0, fifobus.write_data.max) for _ in range(ntx)]
yield spibus.writeread(0x55)
yield spibus.writeread(0xAA)
yield spibus.writeread(0xCE)
assert spibus.get_read_data() == 0x55
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xAA
yield spibus.writeread(0x01)
assert spibus.get_read_data() == 0xCE
raise StopSimulation
@always_comb
def tb_fifo_loopback():
if not fifobus.full:
fifobus.write.next = not fifobus.empty
fifobus.read.next = not fifobus.empty
fifobus.write_data.next = fifobus.read_data
# monitors
@always_comb
def tbmon():
data.next = fifobus.read_data
rd.next = fifobus.read
wr.next = fifobus.write
full.next = fifobus.full
empty.next = fifobus.empty
return tbdut, tbclk, tbstim, tb_fifo_loopback, tbmon
run_testbench(bench_spi_slave, args=args)
def test_elink_io(args=None):
args = tb_default_args(args)
def _bench_elink_io():
@instance
def tbstim():
yield delay(10)
return tbstim
run_testbench(_bench_elink_io, timescale='1ps', args=args)
def test_spi_cso(args=None):
args = tb_default_args(args)
def bench():
@instance
def tbstim():
# @todo: add test stimulus
yield delay(10)
raise StopSimulation
return tbstim
run_testbench(bench, args)
def test_xula_vga(args=None):
args = tb_default_args(args)
resolution = (64, 48,)
refresh_rate = 60
line_rate = 31250
color_depth = (3, 4, 3,)
clock = Clock(0, frequency=12e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
vga = VGA(color_depth=color_depth)
vga_hsync, vga_vsync = Signals(bool(0), 2)
vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3)
vselect = Signal(bool(0))
pxlen, active = Signals(bool(0), 2)
@myhdl.block
def bench():
tbdut = xula_vga(
clock, reset,
vselect, vga_hsync, vga_vsync,
vga_red, vga_green, vga_blue,
pxlen, active,
resolution=resolution, color_depth=color_depth,
refresh_rate=refresh_rate, line_rate=line_rate
)
tbclk = clock.gen()
mdl = VGADisplay(frequency=clock.frequency,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate,
color_depth=color_depth)
tbmdl = mdl.process(glbl, vga)
@instance
def tbstim():
yield delay(100000)
raise StopSimulation
return tbdut, tbclk, tbmdl, tbstim
# run the above stimulus, the above is not self checking it simply
# verifies the code will simulate.
run_testbench(bench, args=args)
portmap = dict(vselect=vselect, hsync=vga_hsync, vsync=vga_vsync,
red=vga_red, green=vga_green, blue=vga_blue,
clock=clock)
# convert the module, check for any conversion errors
tb_convert(xula_vga, **portmap)
def test_elink_io(args=None):
args = tb_default_args(args)
@myhdl.block
def bench_elink_io():
@instance
def tbstim():
yield delay(10)
raise StopSimulation
return tbstim
run_testbench(bench_elink_io, timescale='1ps', args=args)
def test_elink_io(args=None):
args = tb_default_args(args)
@myhdl.block
def bench_elink_io():
@instance
def tbstim():
yield delay(10)
raise StopSimulation
return tbstim
run_testbench(bench_elink_io, timescale='1ps', args=args)
def testbench_nameofwhatsbeingtested(args=None):
""" """
# if no arguments were passed get the default arguments, one of
# the reasons this is done this way is to avoid conflicts with
# the py.test test runner, when executed with py.test no CLI
# arguments are expected (although the "test_*" might set specific
# arguments for a test.
args = tb_default_args(args)
if not hasattr(args, 'num_loops'):
args.num_loops = 10
# create signals, models, etc. that are needed for the various
# stimulus (a testbench may have multiple stimulus tests).
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
sigin = Signal(intbv(0)[8:])
sigout = Signal(intbv(0)[8:])
# create a test/stimulus function, this function is passed
# to the `run_testbench` function. A single function is used
# so the signals in the stimulus can be traced.
@myhdl.block
def bench_nameofwhatsbeingtested():
""" """
# instantiate design under test, etc.
tbdut = some_module(glbl, sigin, sigout)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(30)
yield clock.posedge
# perform stimulus and checking
for ii in range(args.num_loops):
sigin.next = randint(0, 255)
yield clock.posedge # on the edge the new input is capture
yield delay(1) # after the edge the output is available
print(" sigin: {:02X}, sigout: {:02X}".format(
int(sigin), int(sigout)))
assert sigout == sigin
raise StopSimulation
# return the generators (instances() could be used)
return tbdut, tbclk, tbstim
run_testbench(bench_nameofwhatsbeingtested, args=args)
def testbench_nameofwhatsbeingtested(args=None):
""" """
# if no arguments were passed get the default arguments, one of
# the reasons this is done this way is to avoid conflicts with
# the py.test test runner, when executed with py.test no CLI
# arguments are expected (although the "test_*" might set specific
# arguments for a test.
args = tb_default_args(args)
if not hasattr(args, 'num_loops'):
args.num_loops = 10
# create signals, models, etc. that are needed for the various
# stimulus (a testbench may have multiple stimulus tests).
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
sigin = Signal(intbv(0)[8:])
sigout = Signal(intbv(0)[8:])
# create a test/stimulus function, this function is passed
# to the `run_testbench` function. A single function is used
# so the signals in the stimulus can be traced.
@myhdl.block
def bench_nameofwhatsbeingtested():
""" """
# instantiate design under test, etc.
tbdut = some_module(glbl, sigin, sigout)
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(30)
yield clock.posedge
# perform stimulus and checking
for ii in range(args.num_loops):
sigin.next = randint(0, 255)
yield clock.posedge # on the edge the new input is capture
yield delay(1) # after the edge the output is available
print(" sigin: {:02X}, sigout: {:02X}".format(int(sigin), int(sigout)))
assert sigout == sigin
raise StopSimulation
# return the generators (instances() could be used)
return tbdut, tbclk, tbstim
run_testbench(bench_nameofwhatsbeingtested, args=args)
def test_lt24lcd(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
lcd_on = Signal(bool(0))
lcd_resetn = Signal(bool(0))
lcd_csn = Signal(bool(0))
lcd_rs = Signal(bool(0))
lcd_wrn = Signal(bool(0))
lcd_rdn = Signal(bool(0))
lcd_data = Signal(intbv(0)[16:])
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
mvd = LT24LCDDisplay()
@myhdl.block
def bench_lt24lcdsys():
tbdut = mm_lt24lcdsys(
clock, reset, lcd_on, lcd_resetn,
lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data
)
tbvd = mvd.process(glbl, lcd) # LCD display model
tbclk = clock.gen()
@instance
def tbstim():
yield reset.pulse(33)
yield clock.posedge
timeout = 33000
while mvd.update_cnt < 3 and timeout > 0:
yield delay(1000)
timeout -= 1
yield delay(100)
print("{:<10d}: simulation real time {}".format(now(), mvd.get_time()))
raise StopSimulation
return tbdut, tbvd, tbclk, tbstim
run_testbench(bench_lt24lcdsys)
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# convert the generator
inst = prbs_generate(glbl, prbs, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
inst = prbs_check(glbl, prbs, locked, word_count, error_count, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# convert the generator
inst = prbs_generate(glbl, prbs, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
inst = prbs_check(glbl, prbs, locked, word_count, error_count, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
def test_zybo_vga(args=None):
args = tb_default_args(args)
resolution = (80, 60,)
refresh_rate = 60
line_rate = 31250
color_depth = (6, 6, 6,)
clock = Clock(0, frequency=125e6)
glbl = Global(clock)
vga = VGA(color_depth=color_depth)
vga_hsync, vga_vsync = Signals(bool(0), 2)
vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3)
led, btn = Signals(intbv(0)[4:], 2)
@myhdl.block
def bench():
tbdut = zybo_vga(led, btn, vga_red, vga_green, vga_blue,
vga_hsync, vga_vsync, clock,
resolution=resolution, color_depth=color_depth,
refresh_rate=refresh_rate, line_rate=line_rate)
tbclk = clock.gen()
mdl = VGADisplay(frequency=clock.frequency, resolution=resolution,
refresh_rate=refresh_rate, line_rate=line_rate,
color_depth=color_depth)
tbmdl = mdl.process(glbl, vga)
@instance
def tbstim():
yield delay(100000)
raise StopSimulation
return tbdut, tbclk, tbmdl, tbstim
# run the above testbench, the above testbench doesn't functionally
# verify anything only verifies basics.
run_testbench(bench, args=args)
# test conversion
portmap = dict(led=led, btn=btn, vga_red=vga_red, vga_grn=vga_green,
vga_blu=vga_blue, vga_hsync=vga_hsync, vga_vsync=vga_vsync,
clock=clock)
inst = zybo_vga(**portmap)
tb_convert(inst)
def test_device_clock_mgmt(args=None):
args = tb_default_args(args)
if not hasattr(args, 'vendor'):
args.vendor = 'altera'
clockext = Clock(0, frequency=50e6)
resetext = ResetSignal(0, active=0, async=True)
dripple = Signal(bool(0))
status = Signal(intbv(0)[4:])
def _bench_device_pll():
tbdut = top_clock_mgmt_wrap(clockext, resetext, dripple,
status, args)
@always(delay(10*ticks_per_ns))
def tbclk():
clockext.next = not clockext
@instance
def tbstim():
resetext.next = not resetext.active
yield delay(33*ticks_per_ns)
for ii in range(3):
yield dripple.posedge
ts = myhdl.now()
yield dripple.posedge
td = myhdl.now() - ts
yield delay(100*ticks_per_ns)
print(td, 2*ticks_per_ns*1e3)
# assert td == 2 * ticks_per_ns * 1e3
yield delay(100*ticks_per_ns)
raise myhdl.StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_device_pll, args)
myhdl.toVerilog.name = top_clock_mgmt_wrap.__name__ + '_' + args.vendor
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(top_clock_mgmt_wrap, clockext, resetext, dripple, status, args)
def test_device_clock_mgmt(args=None):
args = tb_default_args(args)
if not hasattr(args, 'vendor'):
args.vendor = 'altera'
clockext = Clock(0, frequency=50e6)
resetext = ResetSignal(0, active=0, async=True)
dripple = Signal(bool(0))
status = Signal(intbv(0)[4:])
def _bench_device_pll():
tbdut = top_clock_mgmt_wrap(clockext, resetext, dripple, status, args)
@always(delay(10 * ticks_per_ns))
def tbclk():
clockext.next = not clockext
@instance
def tbstim():
resetext.next = not resetext.active
yield delay(33 * ticks_per_ns)
for ii in range(3):
yield dripple.posedge
ts = myhdl.now()
yield dripple.posedge
td = myhdl.now() - ts
yield delay(100 * ticks_per_ns)
print(td, 2 * ticks_per_ns * 1e3)
# assert td == 2 * ticks_per_ns * 1e3
yield delay(100 * ticks_per_ns)
raise myhdl.StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_device_pll, args)
myhdl.toVerilog.name = top_clock_mgmt_wrap.__name__ + '_' + args.vendor
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(top_clock_mgmt_wrap, clockext, resetext, dripple, status,
args)
def test_parallella_serdes(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=True)
txp = Signal(intbv(0)[6:])
txn = Signal(intbv(0)[6:])
rxp = Signal(intbv(0)[6:])
rxn = Signal(intbv(0)[6:])
leds = Signal(intbv(0)[8:])
@myhdl.block
def bench_serdes():
tbdut = parallella_serdes(clock, txp, txn, rxp, rxn, leds)
tbclk = clock.gen(hticks=10000)
@always_comb
def tblpk():
rxp.next = txp
rxn.next = txn
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
for ii in range(100):
for jj in range(1000):
yield clock.posedge
yield delay(1000)
raise StopSimulation
return tbdut, tbclk, tblpk, tbstim
run_testbench(bench_serdes, timescale='1ps', args=args)
inst = parallella_serdes(
clock, txp, txn, rxp, rxn, leds
)
inst.convert(hdl='Verilog', directory='output', testbench=False)
def test_parallella_serdes(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=True)
txp = Signal(intbv(0)[6:])
txn = Signal(intbv(0)[6:])
rxp = Signal(intbv(0)[6:])
rxn = Signal(intbv(0)[6:])
leds = Signal(intbv(0)[8:])
@myhdl.block
def bench_serdes():
tbdut = parallella_serdes(clock, txp, txn, rxp, rxn, leds)
tbclk = clock.gen(hticks=10000)
@always_comb
def tblpk():
rxp.next = txp
rxn.next = txn
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
for ii in range(100):
for jj in range(1000):
yield clock.posedge
yield delay(1000)
raise StopSimulation
return tbdut, tbclk, tblpk, tbstim
run_testbench(bench_serdes, timescale='1ps', args=args)
inst = parallella_serdes(
clock, txp, txn, rxp, rxn, leds
)
inst.convert(hdl='Verilog', directory='output', testbench=False)
def test_device_clock_mgmt(args=None):
args = tb_default_args(args)
if not hasattr(args, "vendor"):
args.vendor = "altera"
clockext = Clock(0, frequency=50e6)
resetext = ResetSignal(0, active=0, async=True)
dripple = Signal(bool(0))
status = Signal(intbv(0)[4:])
@myhdl.block
def bench_device_pll():
tbdut = top_clock_mgmt_wrap(clockext, resetext, dripple, status, args)
@always(delay(10 * ticks_per_ns))
def tbclk():
clockext.next = not clockext
@instance
def tbstim():
resetext.next = not resetext.active
yield delay(33 * ticks_per_ns)
for ii in range(3):
yield dripple.posedge
ts = myhdl.now()
yield dripple.posedge
td = myhdl.now() - ts
yield delay(100 * ticks_per_ns)
print(td, 2 * ticks_per_ns * 1e3)
# assert td == 2 * ticks_per_ns * 1e3
yield delay(100 * ticks_per_ns)
raise myhdl.StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_device_pll, args=args)
inst = top_clock_mgmt_wrap(clockext, resetext, dripple, status, args)
inst.convert(hdl="Verilog", directory="output")
def test_known_prbs5(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
expected_pattern = (
0xC7,
0xAE,
0x90,
0xE6,
)
@myhdl.block
def bench_prbs5():
tbdut = prbs_generate(glbl, prbs, order=5, initval=0x1F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
for ii, ep in enumerate(expected_pattern):
assert prbs == ep
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_prbs5, timescale='1ps', args=args)
def test_devprim(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
led = Signal(intbv(0))
def _bench_devprim():
tbdut = de0nano_soc_device_prims(clock, reset, led)
tbclk = clock.gen(hticks=10000)
@instance
def tbstim():
print("start simulation")
yield reset.pulse(36)
yield clock.posedge
for ii in range(40):
yield delay(11111)
print("end simulation")
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_devprim, args=args)
def test_devprim(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=0, async=True)
leds = Signal(intbv(0)[4:])
def _bench_devprim():
tbdut = zybo_device_prim(clock, leds, reset)
tbclk = clock.gen(hticks=10000)
@instance
def tbstim():
print("start simulation")
yield reset.pulse(36)
yield clock.posedge
for ii in range(40):
yield delay(11111)
print("end simulation")
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(_bench_devprim, args=args)
def test_devprim(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=0, isasync=True)
leds = Signal(intbv(0)[4:])
@myhdl.block
def bench_devprim():
tbdut = zybo_device_prim(clock, leds, reset)
tbclk = clock.gen(hticks=10000)
@instance
def tbstim():
print("start simulation")
yield reset.pulse(36)
yield clock.posedge
for ii in range(40):
yield delay(11111)
print("end simulation")
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_devprim, args=args)
def test_devprim(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
led = Signal(intbv(0))
@myhdl.block
def bench_devprim():
tbdut = de0nano_soc_device_prims(clock, reset, led)
tbclk = clock.gen(hticks=10000)
@instance
def tbstim():
print("start simulation")
yield reset.pulse(36)
yield clock.posedge
for ii in range(40):
yield delay(11111)
print("end simulation")
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_devprim, args=args)
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog.no_testbench = True
myhdl.toVHDL.directory = 'output'
# convert the generator
myhdl.toVerilog(prbs_generate, glbl, prbs, order=23)
myhdl.toVHDL(prbs_generate, glbl, prbs, order=23)
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
myhdl.toVerilog(prbs_check, glbl, prbs, locked,
word_count, error_count, order=23)
myhdl.toVHDL(prbs_check, glbl, prbs, locked,
word_count, error_count, order=23)
def testbench_to_generic(args=None):
""" Test memory-mapped bus and the mapping to a generic bus
:param args:
:return:
"""
depth = 16 # number of memory address
width = 32 # memory-mapped bus data width
maxval = 2**width
run = False if args is None else True
args = tb_default_args(args)
if not hasattr(args, 'num_loops'):
args.num_loops = 10
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
if hasattr(args, 'bustype'):
address_width = 18
membus = busmap[args.bustype](glbl, data_width=width,
address_width=address_width)
else:
address_width = int(ceil(log(depth, 2))) + 4
membus = Barebone(glbl, data_width=width,
address_width=address_width)
def bench_to_generic():
tbdut = peripheral_memory(membus, depth=depth)
tbitx = membus.interconnect()
tbclk = clock.gen()
testvals = {}
@instance
def tbstim():
yield reset.pulse(42)
yield clock.posedge
# only testing one peripheral, set the peripheral/slave
# address to the first ...
if isinstance(membus, Barebone):
membus.per_addr.next = 1
peraddr = 0
else:
peraddr = 0x10000
yield clock.posedge
for ii in range(args.num_loops):
randaddr = randint(0, depth-1) | peraddr
randdata = randint(0, maxval-1)
testvals[randaddr] = randdata
yield membus.writetrans(randaddr, randdata)
yield clock.posedge
for addr, data in testvals.items():
yield membus.readtrans(addr)
read_data = membus.get_read_data()
assert read_data == data, "{:08X} != {:08X}".format(read_data,
data)
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbitx, tbclk, tbstim
if run:
run_testbench(bench_to_generic, args=args)
def test_fifo_sync(args=None):
""" verify the synchronous FIFO
"""
if args is None:
args = Namespace(width=8, size=16, name='test')
else:
assert hasattr(args, 'width')
assert hasattr(args, 'size')
args = tb_default_args(args)
reset = ResetSignal(0, active=1, async=True)
clock = Clock(0, frequency=50e6)
glbl = Global(clock, reset)
fbus = FIFOBus(width=args.width)
@myhdl.block
def bench_fifo_sync():
tbdut = fifo_sync(glbl, fbus, size=args.size)
tbclk = clock.gen()
@instance
def tbstim():
fbus.write_data.next = 0xFE
reset.next = reset.active
yield delay(33)
reset.next = not reset.active
for ii in range(5):
yield clock.posedge
# test the normal cases
for num_bytes in range(1, args.size + 1):
# write some bytes
for ii in range(num_bytes):
yield clock.posedge
fbus.write_data.next = ii + 0xCE
fbus.write.next = True
yield clock.posedge
fbus.write.next = False
fbus.write_data.next = 0xFE
# if 16 bytes written make sure FIFO is full
yield clock.posedge
if num_bytes == args.size:
assert fbus.full, "FIFO should be full!"
assert not fbus.empty, "FIFO should not be empty"
# fbus.read.next = True
# yield clock.posedge
for ii in range(5):
yield clock.posedge
if not fbus.empty:
break
for ii in range(num_bytes):
fbus.read.next = True
yield clock.posedge
assert fbus.read_valid
assert fbus.read_data == ii + 0xCE, \
"rdata %x ii %x " % (fbus.read_data, ii + 0xCE)
fbus.read.next = False
yield clock.posedge
assert fbus.empty
raise StopSimulation
w = args.width
write_data, read_data = Signals(intbv(0)[w:], 2)
@always_comb
def tbmon():
write_data.next = fbus.write_data
read_data.next = fbus.read_data
return tbdut, tbclk, tbstim, tbmon
run_testbench(bench_fifo_sync, args=args)
def testbench_to_generic(args=None):
""" Test memory-mapped bus and the mapping to a generic bus
:param args:
:return:
"""
depth = 16 # number of memory address
width = 32 # memory-mapped bus data width
maxval = 2**width
run = False if args is None else True
args = tb_default_args(args)
if not hasattr(args, 'num_loops'):
args.num_loops = 10
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
if hasattr(args, 'bustype'):
address_width = 18
membus = busmap[args.bustype](glbl,
data_width=width,
address_width=address_width)
else:
address_width = int(ceil(log(depth, 2))) + 4
membus = Barebone(glbl, data_width=width, address_width=address_width)
@myhdl.block
def bench_to_generic():
tbdut = peripheral_memory(membus, depth=depth)
tbitx = membus.interconnect()
tbclk = clock.gen()
testvals = {}
@instance
def tbstim():
yield reset.pulse(42)
yield clock.posedge
# only testing one peripheral, set the peripheral/slave
# address to the first ...
if isinstance(membus, Barebone):
membus.per_addr.next = 1
peraddr = 0
else:
peraddr = 0x10000
yield clock.posedge
for ii in range(args.num_loops):
randaddr = randint(0, depth - 1) | peraddr
randdata = randint(0, maxval - 1)
testvals[randaddr] = randdata
yield membus.writetrans(randaddr, randdata)
yield clock.posedge
for addr, data in testvals.items():
yield membus.readtrans(addr)
read_data = membus.get_read_data()
assert read_data == data, "{:08X} != {:08X}".format(
read_data, data)
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbitx, tbclk, tbstim
if run:
run_testbench(bench_to_generic, args=args)
def test_memmap_command_bridge(args=None):
nloops = 37
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
fifobus = FIFOBus()
memmap = Barebone(glbl, data_width=32, address_width=28)
fifobus.clock = clock
def bench_command_bridge():
tbclk = clock.gen()
tbdut = command_bridge(glbl, fifobus, memmap)
readpath, writepath = FIFOBus(), FIFOBus()
readpath.clock = writepath.clock = clock
tbmap = fifobus.assign_read_write_paths(readpath, writepath)
tbftx = fifo_fast(reset, clock, writepath) # user write path
tbfrx = fifo_fast(reset, clock, readpath) # user read path
# @todo: add other bus types
tbmem = memmap_peripheral_bb(clock, reset, memmap)
# save the data read ...
read_value = []
@instance
def tbstim():
yield reset.pulse(32)
fifobus.read.next = False
fifobus.write.next = False
assert not fifobus.full
assert fifobus.empty
assert fifobus.read_data == 0
fifobus.write_data.next = 0
try:
# test a single address
pkt = CommandPacket(True, 0x0000)
yield pkt.put(readpath)
yield pkt.get(writepath, read_value, [0])
pkt = CommandPacket(False, 0x0000, [0x5555AAAA])
yield pkt.put(readpath)
yield pkt.get(writepath, read_value, [0x5555AAAA])
# test a bunch of random addresses
for ii in range(nloops):
randaddr = randint(0, (2**20)-1)
randdata = randint(0, (2**32)-1)
pkt = CommandPacket(False, randaddr, [randdata])
yield pkt.put(readpath)
yield pkt.get(writepath, read_value, [randdata])
except Exception as err:
print("Error: {}".format(str(err)))
traceback.print_exc()
yield delay(2000)
raise StopSimulation
wp_read, wp_valid = Signals(bool(0), 2)
wp_read_data = Signal(intbv(0)[8:])
wp_empty, wp_full = Signals(bool(0), 2)
@always_comb
def tbmon():
wp_read.next = writepath.read
wp_read_data.next = writepath.read_data
wp_valid.next = writepath.read_valid
wp_full.next = writepath.full
wp_empty.next = writepath.empty
return tbclk, tbdut, tbmap, tbftx, tbfrx, tbmem, tbstim, tbmon
run_testbench(bench_command_bridge, args=args)
def test_emesh_fifo(args=None):
"""
"""
args = tb_default_args(args)
clock_a, clock_b = Signal(bool(0)), Signal(bool(0))
reset = ResetSignal(0, active=1, async=False)
emesh_a, emesh_b = EMesh(clock_a), EMesh(clock_b)
input_data, output_data = [], []
@always(delay(2500))
def tbclka():
clock_a.next = not clock_a
@always(delay(1300))
def tbclkb():
clock_b.next = not clock_b
def _bench_emesh_fifo():
tbdut = emesh_fifo(reset, emesh_a, emesh_b)
@instance
def tbstim():
yield delay(1111)
for _ in range(5):
yield clock_a.posedge
# push a single packet and verify receipt on the other side
yield emesh_a.write(0xDEEDA5A5, 0xDECAFBAD, 0xC0FFEE)
input_data.append(EMeshSnapshot(emesh_a))
for _ in range(10):
yield clock_b.posedge
assert len(output_data) == 1
assert output_data[0] == input_data[0]
raise myhdl.StopSimulation
@always(clock_b.posedge)
def tbcap():
if emesh_b.txwr.access or emesh_b.txrd.access or emesh_b.txrr.access:
print("output packet: {}".format(emesh_b))
output_data.append(EMeshSnapshot(emesh_b))
if emesh_a.txwr.access or emesh_a.txwr.data != 0:
print("{}".format(emesh_a))
# monitor an emesh (interface tracing limitations)
emesh_a_access = Signal(bool(0))
emesh_a_data = Signal(intbv(0)[32:0])
emesh_b_access = Signal(bool(0))
emesh_b_data = Signal(intbv(0)[32:0])
cm = Signal(modbv(0)[8:])
@always(emesh_b.clock.posedge)
def tbmon():
cm.next = cm + 1
emesh_a_access.next = emesh_a.txwr.access
emesh_a_data.next = emesh_a.txwr.data
emesh_b_access.next = emesh_b.txwr.access
emesh_b_data.next = emesh_b.txwr.data
return tbclka, tbclkb, tbcap, tbmon, tbdut, tbstim
run_testbench(_bench_emesh_fifo, timescale="1ps", args=args)
def test_emesh_fifo(args=None):
"""
"""
args = tb_default_args(args)
clock_a, clock_b = Signal(bool(0)), Signal(bool(0))
reset = ResetSignal(0, active=1, async=False)
emesh_a, emesh_b = EMesh(clock_a), EMesh(clock_b)
input_data, output_data = [], []
@always(delay(2500))
def tbclka():
clock_a.next = not clock_a
@always(delay(1300))
def tbclkb():
clock_b.next = not clock_b
def bench_emesh_fifo():
tbdut = emesh_fifo(reset, emesh_a, emesh_b)
@instance
def tbstim():
yield delay(1111)
for _ in range(5):
yield clock_a.posedge
# push a single packet and verify receipt on the other side
yield emesh_a.write(0xDEEDA5A5, 0xDECAFBAD, 0xC0FFEE)
input_data.append(EMeshSnapshot(emesh_a))
for _ in range(10):
yield clock_b.posedge
assert len(output_data) == 1
assert output_data[0] == input_data[0]
raise myhdl.StopSimulation
@always(clock_b.posedge)
def tbcap():
if emesh_b.txwr.access or emesh_b.txrd.access or emesh_b.txrr.access:
print("output packet: {}".format(emesh_b))
output_data.append(EMeshSnapshot(emesh_b))
if emesh_a.txwr.access or emesh_a.txwr.data != 0:
print("{}".format(emesh_a))
# monitor an emesh (interface tracing limitations)
emesh_a_access = Signal(bool(0))
emesh_a_data = Signal(intbv(0)[32:0])
emesh_b_access = Signal(bool(0))
emesh_b_data = Signal(intbv(0)[32:0])
cm = Signal(modbv(0)[8:])
@always(emesh_b.clock.posedge)
def tbmon():
cm.next = cm + 1
emesh_a_access.next = emesh_a.txwr.access
emesh_a_data.next = emesh_a.txwr.data
emesh_b_access.next = emesh_b.txwr.access
emesh_b_data.next = emesh_b.txwr.data
return tbclka, tbclkb, tbcap, tbmon, tbdut, tbstim
run_testbench(bench_emesh_fifo, timescale='1ps', args=args)
def test_spi_controller_cso(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
spibus = SPIBus()
# a FIFOBus to push-pull data from the SPI controller
fifobus = FIFOBus(width=8)
# control-status object for the SPI controller
cso = spi_controller.cso()
spiee = SPIEEPROM()
asserr = Signal(bool(0))
@myhdl.block
def bench_spi_cso():
spi_controller.debug = True # enable debug monitors
tbdut = spi_controller(glbl, spibus, fifobus, cso=cso)
tbeep = spiee.process(clock, reset, spibus)
tbclk = clock.gen(hticks=5)
@instance
def tbstim():
yield reset.pulse(33)
yield delay(100)
yield clock.posedge
try:
# enable the SPI core
cso.enable.next = True
cso.bypass_fifo.next = True
cso.loopback.next = True
# write to the transmit FIFO
values = (0x02, 0x00, 0x00, 0x00, 0x55)
for data in values:
cso.tx_byte.next = data
cso.tx_write.next = True
yield clock.posedge
cso.tx_write.next = False
while cso.tx_fifo_count > 0:
yield delay(100)
while cso.rx_fifo_count < 5:
yield delay(100)
ii, nticks = 0, 0
while ii < len(values):
if cso.rx_empty:
cso.rx_read.next = False
else:
cso.rx_read.next = True
if cso.rx_byte_valid:
assert values[ii] == cso.rx_byte, \
"{:<4d}: data mismatch, {:02X} != {:02X}".format(
ii, int(values[ii]), int(cso.rx_byte))
ii += 1
nticks = 0
yield clock.posedge, cso.rx_empty.posedge
cso.rx_read.next = False
if nticks > 30:
raise TimeoutError
nticks += 1
cso.rx_read.next = False
yield clock.posedge
except AssertionError as err:
asserr.next = True
print("@E: assertion {}".format(err))
yield delay(100)
traceback.print_exc()
raise err
raise StopSimulation
# monitor signals for debugging
tx_write, rx_read = Signals(bool(0), 2)
@always_comb
def tbmon():
rx_read.next = cso.rx_read
tx_write.next = cso.tx_write
return tbdut, tbeep, tbclk, tbstim, tbmon
run_testbench(bench_spi_cso, args=args)
def test_spi_memory_mapped(args=None):
args = tb_default_args(args)
base_address = ba = 0x400
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
regbus = Wishbone(glbl)
fifobus = FIFOBus(size=16)
spiee = SPIEEPROM()
spibus = SPIBus()
asserr = Signal(bool(0))
@myhdl.block
def bench_spi():
tbdut = spi_controller(glbl, spibus, fifobus=fifobus, mmbus=regbus)
tbeep = spiee.gen(clock, reset, spibus)
tbclk = clock.gen(hticks=5)
# grab all the register file outputs
tbmap = regbus.interconnect()
# get a reference to the SPI register file
rf = regbus.regfiles['SPI_000']
# dumpy the registers for the SPI peripheral
print("SPI register file")
for name, reg in rf.registers.items():
print(" {0} {1:04X} {2:04X}".format(name, reg.addr, int(reg)))
print("")
@instance
def tbstim():
yield reset.pulse(33)
yield delay(100)
yield clock.posedge
try:
# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# loop through the registers and check the default
# values, these are the offset values.
for addr, sig in rf.roregs:
yield regbus.readtrans(addr + ba)
assert regbus.get_read_data() == int(sig), \
"Invalid read-only value"
for addr, sig in rf.rwregs:
# need to skip the FIFO read / write
if addr in (
rf.sptx.addr,
rf.sprx.addr,
):
pass
else:
yield regbus.readtrans(addr + ba)
assert regbus.get_read_data() == int(sig), \
"Invalid default value"
# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# enable the system
print("enable the SPI core")
yield regbus.writetrans(rf.spst.addr,
0x02) # register data drives fifo
yield regbus.writetrans(rf.spcr.addr,
0x9A) # default plus enable (98 + 02)
print("write to the transmit register")
for data in (0x02, 0x00, 0x00, 0x00, 0x55):
print("\nwriting to sptx {:02x}".format(data))
yield regbus.writetrans(rf.sptx.addr, data)
print("")
yield regbus.readtrans(rf.sptc.addr)
print("TX FIFO count {}".format(regbus.get_read_data()))
yield regbus.readtrans(rf.sprc.addr)
print("RX FIFO count {}".format(regbus.get_read_data()))
yield delay(1000)
print("wait for return bytes")
for ii in range(1000):
yield regbus.readtrans(rf.sprc.addr)
if regbus.get_read_data() == 5:
break
yield delay(10)
# verify bytes received and not timeout
print("RX FIFO count {}".format(regbus.get_read_data()))
assert regbus.get_read_data() == 5
print("read the returned bytes")
for ii in range(5):
yield regbus.readtrans(rf.sprx.addr)
print("spi readback {0}".format(regbus.get_read_data()))
except Exception as err:
print("@W: exception {0}".format(err))
yield delay(100)
traceback.print_exc()
raise err
yield delay(100)
raise StopSimulation
return tbstim, tbdut, tbeep, tbclk, tbmap
run_testbench(bench_spi, args=args)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
led = Signal(intbv(0)[8:])
sw = Signal(intbv(1)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uartmdl = UARTModel()
baudrate = uartmdl.baudrate
baudticks = int((1/baudrate) / 1e-9)
def _bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = atlys_blinky_host(clock, reset, led, sw, pmod,
uart_tx, uart_rx)
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
# test loopback
for ii in range(5):
wb = randint(0, 255)
uartmdl.write(wb)
# wait for the send (return)
yield delay(baudticks*(8+2) + 2*baudticks)
rb = uartmdl.read()
assert rb == wb
sw.next = 0
yield delay(100)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = baudticks * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise Exception("TimeoutError")
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(_bench_ibh, args=args)
myhdl.toVerilog.directory = 'output'
myhdl.toVerilog(atlys_blinky_host, clock, reset,
led, sw, pmod,
uart_tx, uart_rx)
def test_fifo_sync(args=None):
""" verify the synchronous FIFO
"""
if args is None:
args = Namespace(width=8, size=16, name='test')
else:
assert hasattr(args, 'width')
assert hasattr(args, 'size')
args = tb_default_args(args)
reset = ResetSignal(0, active=1, async=True)
clock = Clock(0, frequency=50e6)
glbl = Global(clock, reset)
fbus = FIFOBus(width=args.width)
@myhdl.block
def bench_fifo_sync():
tbdut = fifo_sync(glbl, fbus, size=args.size)
tbclk = clock.gen()
@instance
def tbstim():
fbus.write_data.next = 0xFE
reset.next = reset.active
yield delay(33)
reset.next = not reset.active
for ii in range(5):
yield clock.posedge
# test the normal cases
for num_bytes in range(1, args.size+1):
# write some bytes
for ii in range(num_bytes):
yield clock.posedge
fbus.write_data.next = ii + 0xCE
fbus.write.next = True
yield clock.posedge
fbus.write.next = False
fbus.write_data.next = 0xFE
# if 16 bytes written make sure FIFO is full
yield clock.posedge
if num_bytes == args.size:
assert fbus.full, "FIFO should be full!"
assert not fbus.empty, "FIFO should not be empty"
# fbus.read.next = True
# yield clock.posedge
for ii in range(5):
yield clock.posedge
if not fbus.empty:
break
for ii in range(num_bytes):
fbus.read.next = True
yield clock.posedge
assert fbus.read_valid
assert fbus.read_data == ii + 0xCE, \
"rdata %x ii %x " % (fbus.read_data, ii + 0xCE)
fbus.read.next = False
yield clock.posedge
assert fbus.empty
raise StopSimulation
w = args.width
write_data, read_data = Signals(intbv(0)[w:], 2)
@always_comb
def tbmon():
write_data.next = fbus.write_data
read_data.next = fbus.read_data
return tbdut, tbclk, tbstim, tbmon
run_testbench(bench_fifo_sync, args=args)
def test_lt24lcd_driver(args=None):
args = tb_default_args(args)
run_testbench(bench_lt24lcd_driver, args=args)