def tbstim(): yield reset.pulse(32) try: # test a single address pkt = CommandPacket(True, 0x0000) yield pkt.put(fbtx) yield pkt.get(fbrx, read_value, [0]) pkt = CommandPacket(False, 0x0000, [0x5555AAAA]) yield pkt.put(fbtx) yield pkt.get(fbrx, read_value, [0x5555AAAA]) # test a bunch of random addresses for ii in range(nloops): randaddr = randint(0, (2**20)-1) randdata = randint(0, (2**32)-1) pkt = CommandPacket(False, randaddr, [randdata]) yield pkt.put(fbtx) yield pkt.get(fbrx, read_value, [randdata]) except Exception as err: print("Error: {}".format(str(err))) traceback.print_exc() yield delay(2000) raise StopSimulation
def tbstim(): yield reset.pulse(32) fifobus.read.next = False fifobus.write.next = False assert not fifobus.full assert fifobus.empty assert fifobus.read_data == 0 fifobus.write_data.next = 0 try: # test a single address pkt = CommandPacket(True, 0x0000) yield pkt.put(readpath) yield pkt.get(writepath, read_value, [0]) pkt = CommandPacket(False, 0x0000, [0x5555AAAA]) yield pkt.put(readpath) yield pkt.get(writepath, read_value, [0x5555AAAA]) # test a bunch of random addresses for ii in range(nloops): randaddr = randint(0, (2**20)-1) randdata = randint(0, (2**32)-1) pkt = CommandPacket(False, randaddr, [randdata]) yield pkt.put(readpath) yield pkt.get(writepath, read_value, [randdata]) except Exception as err: print("Error: {}".format(str(err))) traceback.print_exc() yield delay(2000) raise StopSimulation
def tbstim(): yield delay(1000) # send a write that should enable all five LEDs pkt = CommandPacket(False, address=0x20, vals=[0xFF]) for bb in pkt.rawbytes: uartmdl.write(bb) waitticks = int((1 / 115200.) / 1e-9) * 10 * 28 yield delay(waitticks) timeout = 100 yield delay(waitticks) # get the response packet for ii in range(PACKET_LENGTH): rb = uartmdl.read() while rb is None and timeout > 0: yield clock.posedge rb = uartmdl.read() timeout -= 1 if rb is None: raise TimeoutError # the last byte should be the byte written assert rb == 0xFF yield delay(1000) raise StopSimulation
def tbstim(): yield reset.pulse(33) yield delay(1000) # test loopback for ii in range(5): wb = randint(0, 255) uartmdl.write(wb) # wait for the send (return) yield delay(baudticks * (8 + 2) + 2 * baudticks) rb = uartmdl.read() assert rb == wb sw.next = 0 yield delay(100) # send a write that should enable all five LEDs pkt = CommandPacket(False, address=0x20, vals=[0xFF]) for bb in pkt.rawbytes: uartmdl.write(bb) waitticks = baudticks * 10 * 28 yield delay(waitticks) timeout = 100 yield delay(waitticks) # get the response packet for ii in range(PACKET_LENGTH): rb = uartmdl.read() while rb is None and timeout > 0: yield clock.posedge rb = uartmdl.read() timeout -= 1 if rb is None: raise Exception("TimeoutError") # the last byte should be the byte written assert rb == 0xFF yield delay(1000) raise StopSimulation
def tbstim(): yield reset.pulse(32) try: # test a single address pkt = CommandPacket(True, 0x0000) yield pkt.put(fbtx) yield pkt.get(fbrx, read_value, [0]) pkt = CommandPacket(False, 0x0000, [0x5555AAAA]) yield pkt.put(fbtx) yield pkt.get(fbrx, read_value, [0x5555AAAA]) # test a bunch of random addresses for ii in range(nloops): randaddr = randint(0, (2**20) - 1) randdata = randint(0, (2**32) - 1) pkt = CommandPacket(False, randaddr, [randdata]) yield pkt.put(fbtx) yield pkt.get(fbrx, read_value, [randdata]) except Exception as err: print("Error: {}".format(str(err))) traceback.print_exc() yield delay(2000) raise StopSimulation
def tbstim(): yield reset.pulse(32) fifobus.read.next = False fifobus.write.next = False assert not fifobus.full assert fifobus.empty assert fifobus.read_data == 0 fifobus.write_data.next = 0 try: # test a single address pkt = CommandPacket(True, 0x0000) yield pkt.put(readpath) yield pkt.get(writepath, read_value, [0]) pkt = CommandPacket(False, 0x0000, [0x5555AAAA]) yield pkt.put(readpath) yield pkt.get(writepath, read_value, [0x5555AAAA]) # test a bunch of random addresses for ii in range(nloops): randaddr = randint(0, (2**20) - 1) randdata = randint(0, (2**32) - 1) pkt = CommandPacket(False, randaddr, [randdata]) yield pkt.put(readpath) yield pkt.get(writepath, read_value, [randdata]) except Exception as err: print("Error: {}".format(str(err))) traceback.print_exc() yield delay(2000) raise StopSimulation