def top_serdes_wrap(clockext, resetext,
sero_p, sero_n, seri_p, seri_n,
args=None):
"""
"""
clkmgmt = ClockManagement(clockext, reset=resetext,
output_frequencies=(125e6, 1e9))
clkmgmt.vendor = args.vendor
# @todo: add external_reset_sync module
def top_serdes_wrap(clockext,
resetext,
sero_p,
sero_n,
seri_p,
seri_n,
args=None):
"""
"""
clkmgmt = ClockManagement(clockext,
reset=resetext,
output_frequencies=(125e6, 1e9))
clkmgmt.vendor = args.vendor
def top_clock_mgmt_wrap(clockext, resetext, dripple, status, args):
# note: the model will have errors for many frequencies the test
# will only work for rational periods (inverse of the freq).
clkmgmt = ClockManagement(clockext,
reset=resetext,
output_frequencies=(
125e6,
200e6,
))
clkmgmt.vendor = args.vendor
# @todo: add external_reset_sync module
# rst_inst = external_reset_sync(clockext, resetext, reset)
# create the pll instance
pll_inst = device_clock_mgmt(clkmgmt)
clockcsr = Signal(bool(0))
clockdat = Signal(bool(0))
dcnt = Signal(intbv(0, min=0, max=int(clkmgmt.clocks[0].frequency / 1e6)))
dmax = dcnt.max
@always_comb
def beh_clock_assign():
clockcsr.next = clkmgmt.clocksout[0]
clockdat.next = clkmgmt.clocksout[1]
@always(clockext.posedge)
def beh_assign():
clkmgmt.enable.next = True
@always_seq(clockcsr.posedge, reset=resetext)
def beh_cnt():
if dcnt == dmax - 1:
dcnt.next = 0
dripple.next = not dripple
else:
dcnt.next = dcnt + 1
@always_seq(clockdat.posedge, reset=resetext)
def beh_led_drv():
status.next[0] = clkmgmt.locked
return pll_inst, beh_assign, beh_clock_assign, beh_cnt, beh_led_drv
def top_clock_mgmt_wrap(clockext, resetext, dripple, status, args):
# note: the model will have errors for many frequencies the test
# will only work for rational periods (inverse of the freq).
clkmgmt = ClockManagement(clockext, reset=resetext,
output_frequencies=(125e6, 200e6,))
clkmgmt.vendor = args.vendor
# @todo: add external_reset_sync module
# rst_inst = external_reset_sync(clockext, resetext, reset)
# create the pll instance
pll_inst = device_clock_mgmt(clkmgmt)
clockcsr = Signal(bool(0))
clockdat = Signal(bool(0))
dcnt = Signal(intbv(0, min=0, max=int(clkmgmt.clocks[0].frequency/1e6)))
dmax = dcnt.max
@always_comb
def beh_clock_assign():
clockcsr.next = clkmgmt.clocksout[0]
clockdat.next = clkmgmt.clocksout[1]
@always(clockext.posedge)
def beh_assign():
clkmgmt.enable.next = True
@always_seq(clockcsr.posedge, reset=resetext)
def beh_cnt():
if dcnt == dmax-1:
dcnt.next = 0
dripple.next = not dripple
else:
dcnt.next = dcnt + 1
@always_seq(clockdat.posedge, reset=resetext)
def beh_led_drv():
status.next[0] = clkmgmt.locked
return pll_inst, beh_assign, beh_clock_assign, beh_cnt, beh_led_drv
