def __init__(self):
c_pci_data_width = 128
num_chnls = 3
self.wordsize = 32
self.ptrsize = 64
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
# instantiate test "memory" module that responds to page fetch/writeback requests
self.submodules.channelsplitter = riffa.ChannelSplitter(
combined_interface_tx, combined_interface_rx)
tx0, rx0 = self.channelsplitter.get_channel(0)
tx1, rx1 = self.channelsplitter.get_channel(1)
self.submodules.tbmem = TBMemory(tx0,
rx0,
tx1,
rx1,
c_pci_data_width=c_pci_data_width,
init_fn=generate_data)
# instantiate design under test
self.submodules.dut = count.Count(
combined_interface_rx=combined_interface_rx,
combined_interface_tx=combined_interface_tx,
c_pci_data_width=c_pci_data_width,
wordsize=self.wordsize,
ptrsize=self.ptrsize,
drive_clocks=False)
# channel to send args / receive results
# remember rx/tx from FPGA side -> write to rx, read from tx
self.tx, self.rx = self.channelsplitter.get_channel(2)
def __init__(self):
self.c_pci_data_width = c_pci_data_width = 128
self.ptrsize = 64
self.wordsize = 32
self.pagesize = 4096
num_chnls = 2
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
self.submodules.dut = virtmem.VirtmemWrapper(
combined_interface_rx=combined_interface_rx,
combined_interface_tx=combined_interface_tx,
c_pci_data_width=c_pci_data_width,
wordsize=self.wordsize,
ptrsize=self.ptrsize,
drive_clocks=False)
self.submodules.channelsplitter = riffa.ChannelSplitter(
combined_interface_tx, combined_interface_rx)
tx0, rx0 = self.channelsplitter.get_channel(0)
tx1, rx1 = self.channelsplitter.get_channel(1)
self.submodules.tbmem = TBMemory(tx0,
rx0,
tx1,
rx1,
c_pci_data_width=c_pci_data_width,
wordsize=self.wordsize,
ptrsize=self.ptrsize,
init_fn=generate_data_fn(
self.wordsize))
def __init__(self):
c_pci_data_width = 128
wordsize = 32
ptrsize = 64
npagesincache = 4
pagesize = 4096
memorywidth = max(c_pci_data_width, wordsize)
memorysize = npagesincache * pagesize * 8 // memorywidth
self.specials.mem = Memory(
memorywidth,
memorysize,
init=[i + 0xABBA for i in range(memorysize)])
self.specials.rd_port = rd_port = self.mem.get_port(has_re=True)
self.specials.wr_port = wr_port = self.mem.get_port(
write_capable=True, we_granularity=min(wordsize, c_pci_data_width))
num_chnls = 2
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
self.submodules.channelsplitter = riffa.ChannelSplitter(
combined_interface_tx, combined_interface_rx)
tx0, rx0 = self.channelsplitter.get_channel(0)
tx1, rx1 = self.channelsplitter.get_channel(1)
self.submodules.dut = PageTransferrer(
rx0,
tx0,
rx1,
tx1,
self.rd_port,
self.wr_port,
c_pci_data_width=c_pci_data_width,
wordsize=wordsize,
ptrsize=ptrsize,
npagesincache=npagesincache,
pagesize=pagesize)
self.submodules.tbmem = TBMemory(tx0,
rx0,
tx1,
rx1,
c_pci_data_width=c_pci_data_width)
def __init__(self): c_pci_data_width = 128 num_chnls = 3 combined_interface_tx = riffa.Interface(data_width=c_pci_data_width, num_chnls=num_chnls) combined_interface_rx = riffa.Interface(data_width=c_pci_data_width, num_chnls=num_chnls) self.submodules.dut = usercode.UserCode(combined_interface_rx=combined_interface_rx, combined_interface_tx=combined_interface_tx, c_pci_data_width=c_pci_data_width, drive_clocks=False) self.submodules.channelsplitter = riffa.ChannelSplitter(combined_interface_tx, combined_interface_rx) tx0, rx0 = self.channelsplitter.get_channel(0) tx1, rx1 = self.channelsplitter.get_channel(1) tx2, rx2 = self.channelsplitter.get_channel(2) data_to_send = [0x604000, 0x604004, 0x597a004, 0xfffe000, 0x8, 0x45600c, 0x604000, 0x604008] self.submodules.writer = Writer(rx2, data_to_send) self.submodules.reader = Reader(tx2, [generate_data(x) for x in data_to_send]) self.submodules.tbmem = TBMemory(tx0, rx0, tx1, rx1, c_pci_data_width=c_pci_data_width, init_fn=generate_data)
def __init__(self):
c_pci_data_width = 128
num_chnls = 3
combined_interface_tx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
combined_interface_rx = riffa.Interface(data_width=c_pci_data_width,
num_chnls=num_chnls)
self.submodules.dut = whoosh.Whoosh(
combined_interface_rx=combined_interface_rx,
combined_interface_tx=combined_interface_tx,
c_pci_data_width=c_pci_data_width,
drive_clocks=False)
self.submodules.channelsplitter = riffa.ChannelSplitter(
combined_interface_tx, combined_interface_rx)
tx0, rx0 = self.channelsplitter.get_channel(0)
tx1, rx1 = self.channelsplitter.get_channel(1)
tx2, rx2 = self.channelsplitter.get_channel(2)
xy_range = 4096
self.data_to_send = [0x604000, xy_range]
self.results = [
functools.reduce(operator.xor, (generate_data((x + i) << 2)
for i in range(3)), 0)
for x in range(xy_range - 2)
] + [generate_data((xy_range - 2) << 2)
] + [generate_data((xy_range - 1) << 2)]
self.submodules.writer = Writer(rx2, self.data_to_send)
self.submodules.reader = Reader(tx2, [xy_range])
self.submodules.tbmem = TBMemory(tx0,
rx0,
tx1,
rx1,
c_pci_data_width=c_pci_data_width,
init_fn=generate_data)