class TestGeneral(unittest.TestCase):
def setUp(self): #run before each test
self.FileIO = FileIO()
self.FileIO.Init("FileIO.csv")
def test_write(self):
self.FileIO.write("Hello World Test_FileIO.py")
self.FileIO.write_raw("Hello World Test_FileIO.py Raw")
def test_readcsv(self):
data = self.FileIO.readcsv()
for i, line in enumerate(data):
print("%d:%s" % (i, ",".join(data[i])))
self.assertEqual("as" + "df", "asdf")
def test_read(self):
data = self.FileIO.read()
for i, line in enumerate(data):
print("%d:%s" % (i, ",".join(line)))
self.assertTrue('FOO'.isupper())
self.assertFalse('Foo'.isupper())
def tearDown(self):
pass
class TestGeneral(unittest.TestCase):
def setUp(self): #Run before each test
self.FileIO = FileIO()
self.FileIO.Init("FileIO.csv")
self.FileIO.debug = 0
def tearDown(self): #Run after each test
self.FileIO.Outfile.close()
###############################################################################
### </Test>
###############################################################################
def test_write(self):
try:
self.FileIO.write("test_write,write") #Append Date
self.FileIO.write_raw("test_write,write_raw") #No Date
except:
self.assertTrue(1) #FAIL
def test_readcsv(self):
self.FileIO.write('testreadcsv,spam,ham,eggs')
data = self.FileIO.readcsv() #Read as 2D Table
size = len(data)
self.assertEqual(data[size-1][3],'ham')
def test_read(self):
self.FileIO.write_raw('testread,spam,ham,eggs')
data = self.FileIO.read() #Read entire file
size = len(data)
self.assertEqual(data[size-1].strip(),'testread,spam,ham,eggs')
CMW.Init_MeasPower(i)
CMW.Set_VSA_Freq(freq)
CMW.Set_VSA_RefLevl(pwr)
##########################################################
### Code Start
##########################################################
from datetime import datetime
from rssd.FileIO import FileIO
from rssd.RCT.GPRF import RCT
f = FileIO()
f.debug = 0
IArry = f.initread(InpFile).readcsv()
OFile = f.Init(OutFile)
CMW = RCT()
CMW.jav_Open("127.0.0.1")
for port in ports:
CMW.Set_Sys_TxPortLoss(port, 0)
CMW.Set_Sys_RxPortLoss(port, 0)
CMW.Init_VSG()
OFile.write('\nDate,Iter,Freq,Pwr,MPwr,Port,Time,Diff')
for r in range(0, repeat): #Repeatability Loop
print("Loop%d" % r)
for cond in IArry: #Condition Loop
for i in [2]: #Port Loop
freq = float(cond[0])
FreqStart = int(51e9)
FreqStop = int(75e9)
FreqStep = int(1e9)
fSpan = 100e6
SWM_Out = -20
Mixer = 1
##########################################################
### Code Start
##########################################################
from rssd.SMW_Common import VSG
from rssd.FileIO import FileIO
import time
f = FileIO()
DataFile = f.Init(OutFile)
SMW = VSG()
SMW.jav_Open(SMW_IP, f.sFName)
##########################################################
### Instrument Settings
##########################################################
SMW.Set_RFPwr(SWM_Out) #Output Power
SMW.Set_RFState('ON') #Turn RF Output on
f.write(SMW.query('FREQ:MULT:EXT:TYPE?')) #SMZ #
f.write(SMW.query('FREQ:MULT:EXT:SNUM?')) #Serial Num
f.write(SMW.query('FREQ:MULT:EXT:LOAD:VERS?'))
f.write(SMW.query('FREQ:MULT:EXT:FMAX?'))
f.write(SMW.query('FREQ:MULT:EXT:FMIN?'))
f.write(SMW.query('FREQ:MULT:EXT:REV?')) #Revision
