def init_system(self, system): """Initialize a system. Arguments: system -- System to initialize. """ self.create_clk_src(system) system.cpu = self.create_cpus(system.cpu_clk_domain) if _have_kvm_support and \ any([isinstance(c, BaseKvmCPU) for c in system.cpu]): self.init_kvm(system) if self.use_ruby: # Add the ruby specific and protocol specific options parser = optparse.OptionParser() Options.addCommonOptions(parser) Ruby.define_options(parser) (options, args) = parser.parse_args() # Set the default cache size and associativity to be very # small to encourage races between requests and writebacks. options.l1d_size="32kB" options.l1i_size="32kB" options.l2_size="4MB" options.l1d_assoc=4 options.l1i_assoc=2 options.l2_assoc=8 options.num_cpus = self.num_cpus options.num_dirs = 2 bootmem = getattr(system, 'bootmem', None) Ruby.create_system(options, True, system, system.iobus, system._dma_ports, bootmem) # Create a seperate clock domain for Ruby system.ruby.clk_domain = SrcClockDomain( clock = options.ruby_clock, voltage_domain = system.voltage_domain) for i, cpu in enumerate(system.cpu): if not cpu.switched_out: cpu.createInterruptController() cpu.connectCachedPorts(system.ruby._cpu_ports[i]) else: sha_bus = self.create_caches_shared(system) for cpu in system.cpu: self.init_cpu(system, cpu, sha_bus)
for r in drive_sys.mem_ranges] for i in range(len(drive_sys.mem_ctrls)): drive_sys.mem_ctrls[i].port = drive_sys.membus.master drive_sys.init_param = options.init_param return drive_sys # Add options parser = optparse.OptionParser() Options.addCommonOptions(parser) Options.addFSOptions(parser) # Add the ruby specific and protocol specific options if '--ruby' in sys.argv: Ruby.define_options(parser) (options, args) = parser.parse_args() if args: print("Error: script doesn't take any positional arguments") sys.exit(1) # system under test can be any CPU (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) # Match the memories with the CPUs, based on the options for the test system TestMemClass = Simulation.setMemClass(options) if options.benchmark: try:
parser.add_option("--maxloads", metavar="N", default=0, help="Stop after N loads") parser.add_option("--progress", type="int", default=1000, metavar="NLOADS", help="Progress message interval " "[default: %default]") parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers") parser.add_option("--functional", type="int", default=0, help="percentage of accesses that should be functional") parser.add_option("--suppress-func-warnings", action="store_true", help="suppress warnings when functional accesses fail") # # Add the ruby specific and protocol specific options # Ruby.define_options(parser) execfile(os.path.join(config_root, "common", "Options.py")) (options, args) = parser.parse_args() # # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. # options.l1d_size="256B" options.l1i_size="256B" options.l2_size="512B" options.l3_size="1kB" options.l1d_assoc=2 options.l1i_assoc=2
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Nilay Vaish import m5, os, optparse, sys from m5.objects import * m5.util.addToPath('../configs/') from common.Benchmarks import SysConfig from common import FSConfig from ruby import Ruby from common import Options # Add the ruby specific and protocol specific options parser = optparse.OptionParser() Options.addCommonOptions(parser) Ruby.define_options(parser) (options, args) = parser.parse_args() # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. options.l1d_size="32kB" options.l1i_size="32kB" options.l2_size="4MB" options.l1d_assoc=2 options.l1i_assoc=2 options.l2_assoc=2 options.num_cpus = 2 #the system mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
default=-1, help="Only send to this destination.\ Set to -1 to disable.") parser.add_argument("--inj-vnet", type=int, default=-1, choices=[-1, 0, 1, 2], help="Only inject in this vnet (0, 1 or 2).\ 0 and 1 are 1-flit, 2 is 5-flit.\ Set to -1 to inject randomly in all vnets.") # # Add the ruby specific and protocol specific options # Ruby.define_options(parser) args = parser.parse_args() cpus = [ GarnetSyntheticTraffic( num_packets_max=args.num_packets_max, single_sender=args.single_sender_id, single_dest=args.single_dest_id, sim_cycles=args.sim_cycles, traffic_type=args.synthetic, inj_rate=args.injectionrate, inj_vnet=args.inj_vnet, precision=args.precision, num_dest=args.num_dirs) \ for i in range(args.num_cpus) ]
for i in range(len(drive_sys.mem_ctrls)): drive_sys.mem_ctrls[i].port = drive_sys.membus.master drive_sys.init_param = options.init_param return drive_sys # Add options parser = optparse.OptionParser() Options.addCommonOptions(parser) Options.addFSOptions(parser) # Add the ruby specific and protocol specific options if '--ruby' in sys.argv: Ruby.define_options(parser) (options, args) = parser.parse_args() if args: print("Error: script doesn't take any positional arguments") sys.exit(1) # system under test can be any CPU (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) # Match the memories with the CPUs, based on the options for the test system TestMemClass = Simulation.setMemClass(options) if options.benchmark: try:
parser.add_option("--pf-type", type="string", help="type of prefetch: "\ "PF_CU, PF_WF, PF_PHASE, PF_STRIDE") parser.add_option("--pf-stride", type="int", help="set prefetch stride") parser.add_option("--numLdsBanks", type="int", default=32, help="number of physical banks per LDS module") parser.add_option("--ldsBankConflictPenalty", type="int", default=1, help="number of cycles per LDS bank conflict") parser.add_option('--fast-forward-pseudo-op', action='store_true', help = 'fast forward using kvm until the m5_switchcpu' ' pseudo-op is encountered, then switch cpus. subsequent' ' m5_switchcpu pseudo-ops will toggle back and forth') parser.add_option('--outOfOrderDataDelivery', action='store_true', default=False, help='enable OoO data delivery in the GM' ' pipeline') Ruby.define_options(parser) #add TLB options to the parser GPUTLBOptions.tlb_options(parser) (options, args) = parser.parse_args() # The GPU cache coherence protocols only work with the backing store setOption(parser, "--access-backing-store") # if benchmark root is specified explicitly, that overrides the search path if options.benchmark_root: benchmark_path = [options.benchmark_root] else: # Set default benchmark search path to current dir benchmark_path = ['.']
parser.add_argument("--requests", metavar="N", default=100, help="Stop after N requests") parser.add_argument("-f", "--wakeup_freq", metavar="N", default=10, help="Wakeup every N cycles") parser.add_argument("--test-type", default="SeriesGetx", choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed", "Invalidate"], help = "Type of test") parser.add_argument("--percent-writes", type=int, default=100, help="percentage of accesses that should be writes") # # Add the ruby specific and protocol specific args # Ruby.define_options(parser) args = parser.parse_args() # # Select the direct test generator # if args.test_type == "SeriesGetx": generator = SeriesRequestGenerator(num_cpus = args.num_cpus, percent_writes = 100) elif args.test_type == "SeriesGets": generator = SeriesRequestGenerator(num_cpus = args.num_cpus, percent_writes = 0) elif args.test_type == "SeriesGetMixed": generator = SeriesRequestGenerator(num_cpus = args.num_cpus, percent_writes = args.percent_writes) elif args.test_type == "Invalidate":
def makeGpuFSSystem(args): # Boot options are standard gem5 options plus: # - Framebuffer device emulation 0 to reduce driver code paths. # - Blacklist amdgpu as it cannot (currently) load in KVM CPU. # - Blacklist psmouse as amdgpu driver adds proprietary commands that # cause gem5 to panic. boot_options = ['earlyprintk=ttyS0', 'console=ttyS0,9600', 'lpj=7999923', 'root=/dev/sda1', 'drm_kms_helper.fbdev_emulation=0', 'modprobe.blacklist=amdgpu', 'modprobe.blacklist=psmouse'] cmdline = ' '.join(boot_options) if MemorySize(args.mem_size) < MemorySize('2GB'): panic("Need at least 2GB of system memory to load amdgpu module") # Use the common FSConfig to setup a Linux X86 System (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(args) bm = SysConfig(disks=[args.disk_image], mem=args.mem_size) system = makeLinuxX86System(test_mem_mode, args.num_cpus, bm, True, cmdline=cmdline) system.workload.object_file = binary(args.kernel) # Set the cache line size for the entire system. system.cache_line_size = args.cacheline_size # Create a top-level voltage and clock domain. system.voltage_domain = VoltageDomain(voltage = args.sys_voltage) system.clk_domain = SrcClockDomain(clock = args.sys_clock, voltage_domain = system.voltage_domain) # Create a CPU voltage and clock domain. system.cpu_voltage_domain = VoltageDomain() system.cpu_clk_domain = SrcClockDomain(clock = args.cpu_clock, voltage_domain = system.cpu_voltage_domain) # Setup VGA ROM region system.shadow_rom_ranges = [AddrRange(0xc0000, size = Addr('128kB'))] # Create specified number of CPUs. GPUFS really only needs one. system.cpu = [TestCPUClass(clk_domain=system.cpu_clk_domain, cpu_id=i) for i in range(args.num_cpus)] if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): system.kvm_vm = KvmVM() # Create AMDGPU and attach to southbridge shader = createGPU(system, args) connectGPU(system, args) # This arbitrary address is something in the X86 I/O hole hsapp_gpu_map_paddr = 0xe00000000 gpu_hsapp = HSAPacketProcessor(pioAddr=hsapp_gpu_map_paddr, numHWQueues=args.num_hw_queues) dispatcher = GPUDispatcher() gpu_cmd_proc = GPUCommandProcessor(hsapp=gpu_hsapp, dispatcher=dispatcher) shader.dispatcher = dispatcher shader.gpu_cmd_proc = gpu_cmd_proc # GPU, HSAPP, and GPUCommandProc are DMA devices system._dma_ports.append(gpu_hsapp) system._dma_ports.append(gpu_cmd_proc) system._dma_ports.append(system.pc.south_bridge.gpu) gpu_hsapp.pio = system.iobus.mem_side_ports gpu_cmd_proc.pio = system.iobus.mem_side_ports system.pc.south_bridge.gpu.pio = system.iobus.mem_side_ports # Create Ruby system using Ruby.py for now Ruby.create_system(args, True, system, system.iobus, system._dma_ports) # Create a seperate clock domain for Ruby system.ruby.clk_domain = SrcClockDomain(clock = args.ruby_clock, voltage_domain = system.voltage_domain) for (i, cpu) in enumerate(system.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = system.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() system.ruby._cpu_ports[i].connectCpuPorts(cpu) # The shader core will be whatever is after the CPU cores are accounted for shader_idx = args.num_cpus system.cpu.append(shader) gpu_port_idx = len(system.ruby._cpu_ports) \ - args.num_compute_units - args.num_sqc \ - args.num_scalar_cache gpu_port_idx = gpu_port_idx - args.num_cp * 2 # Connect token ports. For this we need to search through the list of all # sequencers, since the TCP coalescers will not necessarily be first. Only # TCP coalescers use a token port for back pressure. token_port_idx = 0 for i in range(len(system.ruby._cpu_ports)): if isinstance(system.ruby._cpu_ports[i], VIPERCoalescer): system.cpu[shader_idx].CUs[token_port_idx].gmTokenPort = \ system.ruby._cpu_ports[i].gmTokenPort token_port_idx += 1 wavefront_size = args.wf_size for i in range(args.num_compute_units): # The pipeline issues wavefront_size number of uncoalesced requests # in one GPU issue cycle. Hence wavefront_size mem ports. for j in range(wavefront_size): system.cpu[shader_idx].CUs[i].memory_port[j] = \ system.ruby._cpu_ports[gpu_port_idx].in_ports[j] gpu_port_idx += 1 for i in range(args.num_compute_units): if i > 0 and not i % args.cu_per_sqc: gpu_port_idx += 1 system.cpu[shader_idx].CUs[i].sqc_port = \ system.ruby._cpu_ports[gpu_port_idx].in_ports gpu_port_idx = gpu_port_idx + 1 for i in range(args.num_compute_units): if i > 0 and not i % args.cu_per_scalar_cache: gpu_port_idx += 1 system.cpu[shader_idx].CUs[i].scalar_port = \ system.ruby._cpu_ports[gpu_port_idx].in_ports gpu_port_idx = gpu_port_idx + 1 return system
from ruby import Ruby from common import Options from common import Simulation from common import CacheConfig from common import CpuConfig from common import MemConfig from common.Caches import * from common.cpu2000 import * parser = optparse.OptionParser() Options.addCommonOptions(parser) Options.addSEOptions(parser) if '--ruby' in sys.argv: Ruby.define_options(parser) else: fatal("This test is only for FPGA in Ruby. Please set --ruby.\n") (options, args) = parser.parse_args() if args: print "Error: script doesn't take any positional arguments" sys.exit(1) numThreads = 1 process1 = LiveProcess() process1.pid = 1100; process1.cmd = ['tests/test-progs/polybench-c-4.2/nussinov-fpga']
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5, os, argparse, sys from m5.objects import * m5.util.addToPath('../configs/') from common.Benchmarks import SysConfig from common import FSConfig, SysPaths from ruby import Ruby from common import Options # Add the ruby specific and protocol specific options parser = argparse.ArgumentParser() Options.addCommonOptions(parser) Ruby.define_options(parser) args = parser.parse_args() # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. args.l1d_size = "32kB" args.l1i_size = "32kB" args.l2_size = "4MB" args.l1d_assoc = 2 args.l1i_assoc = 2 args.l2_assoc = 2 args.num_cpus = 2 #the system mdesc = SysConfig(disks=['linux-x86.img']) system = FSConfig.makeLinuxX86System('timing',
def build_test_system(np, simplessd): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, simplessd, options.num_cpus, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, simplessd, options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, ignore_dtb=options.generate_dtb, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in xrange(np) ] if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: gicv2m_range = AddrRange(0x2c1c0000, 0x2c1d0000 - 1) if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave if buildEnv['TARGET_ISA'] in "arm": if options.machine_type == "VExpress_GEM5_V1": test_sys.iobridge = Bridge(delay='50ns', ranges=[gicv2m_range]) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave elif not options.external_memory_system: mem_ranges = list(test_sys.mem_ranges) # Copy list not reference # Bypass MSI/MSI-X if buildEnv['TARGET_ISA'] in "arm": if options.machine_type == "VExpress_GEM5_V1": mem_ranges.append(gicv2m_range) test_sys.iobridge = Bridge(delay='50ns', ranges=mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.fastmem: if TestCPUClass != AtomicSimpleCPU: fatal("Fastmem can only be used with atomic CPU!") if (options.caches or options.l2cache): fatal("You cannot use fastmem in combination with caches!") if options.simpoint_profile: if not options.fastmem: # Atomic CPU checked with fastmem option already fatal( "SimPoint generation should be done with atomic cpu and fastmem" ) if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in xrange(np): if options.fastmem: test_sys.cpu[i].fastmem = True if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) if buildEnv['TARGET_ISA'] in "x86": lapics = [] for i in xrange(np): lapics.append(test_sys.cpu[i].interrupts[0]) test_sys.msi_handler.lapics = lapics return test_sys
parser.add_argument("--maxloads", metavar="N", default=0, help="Stop after N loads") parser.add_argument("--progress", type=int, default=1000, metavar="NLOADS", help="Progress message interval ") parser.add_argument("--num-dmas", type=int, default=0, help="# of dma testers") parser.add_argument("--functional", type=int, default=0, help="percentage of accesses that should be functional") parser.add_argument("--suppress-func-errors", action="store_true", help="suppress panic when functional accesses fail") # # Add the ruby specific and protocol specific options # Ruby.define_options(parser) args = parser.parse_args() # # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. # args.l1d_size="256B" args.l1i_size="256B" args.l2_size="512B" args.l3_size="1kB" args.l1d_assoc=2 args.l1i_assoc=2 args.l2_assoc=2 args.l3_assoc=2
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem(test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory= options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, voltage_domain = test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) else: print("Error: a kernel must be provided to run in full system mode") sys.exit(1) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np)] if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not CpuConfig.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal("SimPoint generation not supported with more than one CPUs") for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if options.bp_type: bpClass = BPConfig.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = \ BPConfig.get_indirect(options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "riscv": test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions, vio_9p=options.vio_9p, bootloader=options.bootloader, ) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if buildEnv['TARGET_ISA'] == 'riscv': test_sys.workload.bootloader = options.kernel elif options.kernel is not None: test_sys.workload.object_file = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if options.bp_type: bpClass = ObjectList.bp_list.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
from ruby import Ruby from common import Options parser = optparse.OptionParser() Options.addCommonOptions(parser) # add the gpu specific options expected by the the gpu and gpu_RfO parser.add_option("-u", "--num-compute-units", type="int", default=8, help="number of compute units in the GPU") parser.add_option("--num-cp", type="int", default=0, help="Number of GPU Command Processors (CP)") parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" "per CU") parser.add_option("--wf-size", type="int", default=64, help="Wavefront size(in workitems)") parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " "WF slots per SIMD") # Add the ruby specific and protocol specific options Ruby.define_options(parser) (options, args) = parser.parse_args() # # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. # options.l1d_size = "256B" options.l1i_size = "256B" options.l2_size = "512B" options.l3_size = "1kB" options.l1d_assoc = 2 options.l1i_assoc = 2 options.l2_assoc = 2 options.l3_assoc = 2
help="number of cycles per LDS bank conflict") parser.add_options("--lds-size", type="int", default=65536, help="Size of the LDS in bytes") parser.add_option('--fast-forward-pseudo-op', action='store_true', help='fast forward using kvm until the m5_switchcpu' ' pseudo-op is encountered, then switch cpus. subsequent' ' m5_switchcpu pseudo-ops will toggle back and forth') parser.add_option("--num-hw-queues", type="int", default=10, help="number of hw queues in packet processor") Ruby.define_options(parser) #add TLB options to the parser GPUTLBOptions.tlb_options(parser) (options, args) = parser.parse_args() # The GPU cache coherence protocols only work with the backing store setOption(parser, "--access-backing-store") # if benchmark root is specified explicitly, that overrides the search path if options.benchmark_root: benchmark_path = [options.benchmark_root] else: # Set default benchmark search path to current dir benchmark_path = ['.']