def check_literal_goodness(Net, Mod):
Wid1 = compute1(Net[1], Mod)
if Wid1 == 0: Wid1 = 32
if Net[0] == 'bin':
Base = 2
Pr = "'b"
elif Net[0] == 'hex':
Base = 16
Pr = "'h"
elif Net[0] == 'dig':
Base = 10
Pr = "'d"
else:
logs.log_err('what ilia? %s' % Net)
Base = 16
Pr = "'?"
Net2 = string.replace(Net[2], '_', '')
Net2 = string.replace(Net2, 'x', '1')
Net2 = string.replace(Net2, 'X', '1')
try:
Lit = int(Net2, Base)
Wid2 = needed_bits(Lit)
except:
logs.log_err('verilog literal %s%s%s %s has strange chars in it' %
(Net[1], Pr, Net[2], Net[1]))
Wid2 = 32
if Wid2 > Wid1:
logs.log_err('verilog literal %s %s%s%s is too wide for width %s' %
(Net, Net[1], Pr, Net[2], Net[1]))
def check_bus_usage(Current, Bus, Wid, Where=0):
if Bus in Current.mems:
return
if Bus not in Current.nets:
logs.log_errx(
106, 'check_bus_usage failed on %s not defined (line=%d)' %
(Bus, Where))
return
Data = Current.nets[Bus]
Wid1 = Data[1]
(H, L) = Wid
if type(Wid1) is not tuple:
logs.log_errx(
107, 'check_bus_usage failed on %s[%s:%s]' % (Bus, Wid[0], Wid[1]))
else:
if Wid1[0] == 'double':
(H1, L1) = Wid1[1]
elif Wid1[0] == 'packed':
H1 = (Wid1[1][0] + 1) * (Wid1[1][0] + 1)
L1 = 0
else:
(H1, L1) = Wid1
HH = compute1(H, Current)
LL = compute1(L, Current)
HH1 = compute1(H1, Current)
LL1 = compute1(L1, Current)
if (type(HH1) is int) and (type(HH) is int) and (HH > HH1):
logs.log_errx(
108,
'check_bus_usage.0 failed on %s[%s:%s]' % (Bus, Wid[0], Wid[1]))
if (type(HH1) is int) and (type(LL) is int) and (LL > HH1):
logs.log_errx(
109,
'check_bus_usage.1 failed on %s[%s:%s]' % (Bus, Wid[0], Wid[1]))
if (type(LL1) is int) and (type(LL) is int) and (LL < LL1):
logs.log_errx(
110,
'check_bus_usage.2 failed on %s[%s:%s]' % (Bus, Wid[0], Wid[1]))
if (type(LL1) is int) and (type(HH) is int) and (HH < LL1):
logs.log_errx(
111,
'check_bus_usage.3 failed on %s[%s:%s]' % (Bus, Wid[0], Wid[1]))
def make_sig_list(Sig,Mod):
if not Sig:
return [Sig]
if (type(Sig)is str):
if Sig in Mod.nets:
Dir,HsLs = Mod.nets[Sig]
if (HsLs==0):
return [Sig]
elif (HsLs[0]=='double'):
H,L = total_width(Mod,HsLs)
res=[]
for II in range(H,-1,-1):
res.append(['subbit',Sig,II])
return res
else:
return make_sig_list(['subbus',Sig,HsLs[0],HsLs[1]],Mod)
if Sig[0]=='\\':
return make_sig_list(Sig[1:],Mod)
if Sig=='$unconnected':
return [Sig]
log_error('sig for flatten %s not found in %s'%(Sig,Mod.Module),True)
return [Sig]
if (type(Sig)is list)and(Sig[0]=='bin'):
return make_sig_list(['const',Sig[1],'b%s'%Sig[2]],Mod)
if (type(Sig)is list)and(Sig[0]=='hex'):
return make_sig_list(['const',Sig[1],'h%s'%Sig[2]],Mod)
if (type(Sig)is list)and(Sig[0]=='const'):
Wid = Mod.compute_int(Sig[1])
if (Wid==1):
return [ ['const',Sig[1],Sig[2]] ]
Base = Sig[2][0]
Data = Sig[2][1:]
if (Base=='b'):
Val = int(Data,2)
elif (Base=='h'):
Val = int(Data,16)
elif (Base=='d'):
Val = int(Data,10)
else:
Val=0
log_error('bad base for const %s"%s'%(Sig[1],Sig[2]))
res=[]
for i in range(Wid):
V = (Val>>i)&1
res.append(['const',1,'b%d'%V])
res.reverse()
return res
if (type(Sig)is list)and(Sig[0]=='subbit'):
Bus = Sig[1]
_,Wid = Mod.nets[Bus]
if (type(Wid)is tuple)and(len(Wid)==3)and(Wid[0]=='double'):
H1 = Mod.compute_int(Wid[1][0])
L1 = Mod.compute_int(Wid[1][1])
H2 = Mod.compute_int(Wid[2][0])
L2 = Mod.compute_int(Wid[2][1])
Pos = Mod.compute_int(Sig[2])
Mul = (H2-L2+1)
res=[]
for i in range(H1,L1-1,-1):
res.append(['subbit',Bus,str(i+Mul*Pos)])
return res
return [Sig]
if (type(Sig)is list)and(Sig[0]=='subbus'):
Bus = Sig[1]
_,Wid = Mod.nets[Bus]
if len(Sig)==3:
H = int(Sig[2][0])
L = int(Sig[2][1])
elif len(Sig)==4:
H = compute1(Sig[2],Mod)
L = compute1(Sig[3],Mod)
else:
log_error('bus indexing failed %s "%s" '%(Bus,Sig))
H=1
L=0
if (type(Wid)is tuple)and(len(Wid)==3)and(Wid[0]=='double'):
H1 = Mod.compute_int(Wid[1][0])
L1 = Mod.compute_int(Wid[1][1])
H2 = Mod.compute_int(Wid[2][0])
L2 = Mod.compute_int(Wid[2][1])
res=[]
Mul = (H2-L2+1)
for JJ in range(H,L-1,-1):
for II in range(H1,L1-1,-1):
res.append(['subbit',Bus,str(II+Mul*JJ)])
return res
else:
res=[]
for i in range(H,L-1,-1):
res += [ ['subbit',Bus,str(i)]]
return res
if (type(Sig)is list)and(Sig[0]=='curly'):
res=[]
for Item in Sig[1:]:
res += make_sig_list(Item,Mod)
return res
log_error('make_sig_list failed on %s'%(str(Sig)))
return [Sig]
def get_width2(Net, Mod):
if type(Net) == types.IntType:
return 32, needed_bits(Net)
if type(Net) == types.StringType:
if Net in Mod.parameters:
XX = get_width2(Mod.parameters[Net], Mod)
return XX
if Net in Mod.localparams:
XX = get_width2(Mod.localparams[Net], Mod)
return XX
if Net in Mod.nets:
(Dir, Wid) = Mod.nets[Net]
if not Wid:
return 1, 1
H = compute1(Wid[0], Mod)
L = compute1(Wid[1], Mod)
return H - L + 1, H - L + 1
if type(Net) == types.ListType:
if Net[0] == '*':
Smax = 0
Smin = 0
for X in Net[1:]:
Ymax, Ymin = get_width2(X, Mod)
Smax += Ymax
Smin += Ymin
return Smax, Smin
if Net[0] == '/':
Smax, Smin = get_width2(Net[1], Mod)
for X in Net[2:]:
Ymax, Ymin = get_width2(X, Mod)
Smax -= Ymax
Smin -= Ymin
return Smax, Smin
if Net[0] in ['>>', '<<']:
Ymax, Ymin = get_width2(Net[1], Mod)
return Ymax, Ymin
if Net[0] in ['+', '-']:
Max = 1
Min = 32
for X in Net[1:]:
Ymax, Ymin = get_width2(X, Mod)
Max = max(Ymax, Max)
Min = min(Ymin, Min)
return Max + 1, Min
if Net[0] in ['!=', '||', '&&', '!', '>', '==', '>=', '<=']:
return 1, 1
if Net[0] in ['~']:
return get_width2(Net[1], Mod)
if Net[0] in ['|', '&', '^']:
if len(Net) == 2:
return 1, 1
Max = 1
Min = 9999
for X in Net[1:]:
Ymax, Ymin = get_width2(X, Mod)
Max = max(Ymax, Max)
Min = min(Ymin, Min)
return Max, Min
if Net[0] in ['hex', 'dig', 'bin']:
if Net[1] == '':
return 32, 1
else:
X = compute1(Net[1], Mod)
check_literal_goodness(Net, Mod)
if X > 0: return X, X
if Net[0] == 'bin':
return 32, len(Net[2])
if Net[0] == 'dig':
return 32, needed_bits(Net[2])
if Net[0] == 'hex':
return 32, len(Net[2]) * 4
if Net[0] == 'question':
W0, W1 = get_width2(Net[2], Mod)
W2, W3 = get_width2(Net[3], Mod)
return max(W0, W2), min(W1, W3)
if Net[0] == 'subbit':
if Net[1] in Mod.mems:
Dir, Wid1, Wid2 = Mod.mems[Net[1]]
H = compute1(Wid1[0], Mod)
L = compute1(Wid1[1], Mod)
return H - L + 1, H - L + 1
return 1, 1
if Net[0] == 'subbus':
if len(Net) == 3:
H = compute1(Net[2][0], Mod)
L = compute1(Net[2][1], Mod)
else:
H = compute1(Net[2], Mod)
L = compute1(Net[3], Mod)
return H - L + 1, H - L + 1
if Net[0] == 'curly':
sum0 = 0
sum1 = 0
if Net[1] == 'repeat':
Many = compute1(Net[2], Mod)
Ymx, Ymn = get_width2(Net[3], Mod)
return Ymx * Many, Ymn * Many
for X in Net[1:]:
Ymx, Ymn = get_width2(X, Mod)
sum0 += Ymx
sum1 += Ymn
return sum0, sum1
if Net[0] == 'repeat':
W0, W1 = get_width2(Net[2], Mod)
Many = compute1(Net[1], Mod)
return W0 * Many, W1 * Many
if Net[0] in ['<', '>', '<=', '=<', '>=', '=>']:
return 1, 1
if Net[0] == 'functioncall':
return 1, 1
logs.log_err('get_width got %s, cannot determine the width' % str(Net))
print traceback.print_stack()
return 1, 1
def get_width2(Net, Mod):
if type(Net) is int:
return 32, needed_bits(Net)
if type(Net) is str:
if Net[0] in '0123456789': return get_width2(eval(Net), Mod)
if Net in Mod.parameters:
XX = get_width2(Mod.parameters[Net], Mod)
return XX
if Net in Mod.localparams:
XX = get_width2(Mod.localparams[Net], Mod)
return XX
if Net in Mod.nets:
(Dir, Wid) = Mod.nets[Net]
if not Wid:
return 1, 1
if Wid[0] in ('packed', 'double'):
H1 = compute1(Wid[1][0], Mod)
L1 = compute1(Wid[1][1], Mod)
H2 = compute1(Wid[2][0], Mod)
L2 = compute1(Wid[2][1], Mod)
WW = (abs(H1 - L1) + 1) * (abs(H2 - L2) + 1)
return WW, WW
H = compute1(Wid[0], Mod)
L = compute1(Wid[1], Mod)
return abs(H - L) + 1, abs(H - L) + 1
if isinstance(Net, (list, tuple)):
if Net[0] == '*':
Smax = 0
Smin = 0
for X in Net[1:]:
Ymax, Ymin = get_width2(X, Mod)
Smax += Ymax
Smin += Ymin
return Smax, Smin
if Net[0] == '/':
Smax, Smin = get_width2(Net[1], Mod)
for X in Net[2:]:
Ymax, Ymin = get_width2(X, Mod)
Smax -= Ymax
Smin -= Ymin
return Smax, Smin
if Net[0] in ['>>', '<<']:
Ymax, Ymin = get_width2(Net[1], Mod)
return Ymax, Ymin
if Net[0] in ['+', '-']:
Max = 1
Min = 32
for X in Net[1:]:
Ymax, Ymin = get_width2(X, Mod)
Max = max(Ymax, Max)
Min = min(Ymin, Min)
return Max + 1, Min
if Net[0] in ['!=', '||', '&&', '!', '>', '==', '>=', '<=']:
return 1, 1
if Net[0] in ['~']:
return get_width2(Net[1], Mod)
if Net[0] in ['|', '&', '^']:
if len(Net) == 2:
return 1, 1
Max = 1
Min = 9999
for X in Net[1:]:
Ymax, Ymin = get_width2(X, Mod)
Max = max(Ymax, Max)
Min = min(Ymin, Min)
return Max, Min
if Net[0] in ['hex', 'dig', 'bin']:
if Net[1] == '':
return 32, 1
else:
X = compute1(Net[1], Mod)
check_literal_goodness(Net, Mod)
if X > 0: return X, X
if Net[0] == 'bin':
return 32, len(Net[2])
if Net[0] == 'dig':
return 32, needed_bits(Net[2])
if Net[0] == 'hex':
return 32, len(Net[2]) * 4
if Net[0] == 'question':
W0, W1 = get_width2(Net[2], Mod)
W2, W3 = get_width2(Net[3], Mod)
return max(W0, W2), min(W1, W3)
if Net[0] == 'subbit':
if (Mod.mems.keys() != []) and (Net[1] in Mod.mems):
Dir, Wid1, Wid2 = Mod.mems[Net[1]]
H = compute1(Wid1[0], Mod)
L = compute1(Wid1[1], Mod)
return H - L + 1, H - L + 1
return 1, 1
if Net[0] == 'subbus':
if len(Net) == 3:
H = compute1(Net[2][0], Mod)
L = compute1(Net[2][1], Mod)
else:
H = compute1(Net[2], Mod)
L = compute1(Net[3], Mod)
return H - L + 1, H - L + 1
if Net[0] == 'curly':
sum0 = 0
sum1 = 0
if Net[1] == 'repeat':
Many = compute1(Net[2], Mod)
Ymx, Ymn = get_width2(Net[3], Mod)
return Ymx * Many, Ymn * Many
for X in Net[1:]:
Ymx, Ymn = get_width2(X, Mod)
sum0 += Ymx
sum1 += Ymn
return sum0, sum1
if Net[0] == 'repeat':
W0, W1 = get_width2(Net[2], Mod)
Many = compute1(Net[1], Mod)
return W0 * Many, W1 * Many
if Net[0] in ['<', '>', '<=', '=<', '>=', '=>']:
return 1, 1
if Net[0] == 'functioncall':
return 1, 1
logs.log_err('rtl_width get_width got %s, cannot determine the width' %
str(Net))
print(traceback.print_stack())
return 1, 1