uart = uartClass.uartClass('tb', Monitors)
uart.baudRate = 5
import axiSlave
axi = axiSlave.axiSlaveClass('tb', Monitors)
import controllerAluka
control = controllerAluka.controllerClass('tb.dut.debugcontroller', Monitors)
control.uart = uart
import sequenceClass
seq = sequenceClass.sequenceClass('tb', Monitors, '', [(uart, 'uart'),
(axi, 'axi'),
(control, 'control')])
def sequence(SeqFname):
Name = logs.bin2string(SeqFname)
logs.log_info('sequence %s' % Name)
seq.Sequence = open(Name).readlines()
seq.workIncludes()
class driverMonitor:
def __init__(self, Path, Monitors):
Monitors.append(self)
self.Path = Path
import os, sys, string, random
import veri
import math
NewName = os.path.expanduser('~')
sys.path.append('%s/verification_libs3' % NewName)
import logs
Monitors = []
cycles = 0
GIVEUP_TIMEOUT = 1000 # how many cycles to run before retirment.
import axiMaster
import sequenceClass
axi = axiMaster.axiMasterClass('tb', -1)
seq = sequenceClass.sequenceClass('tb', Monitors, '', [('axi', axi)], {})
Expecteds = [0]
def axi_clk():
axi.run()
if veri.peek('tb.wvalid') == '1':
wdata = logs.peek('tb.wdata')
Expecteds[-1] += int(math.sqrt(wdata))
wlast = logs.peek('tb.wlast')
if wlast == 1:
Expecteds.append(0)
def pclk():
if veri.peek('tb.pready') == '0':
ma.wait(100)
mb.wait(100)
mc.wait(100)
md.wait(100)
ma.makeRead(1, 1, self.Pref + 0x00001000, 3, self.Code)
mb.makeRead(1, 1, self.Pref + 0x00002000, 3, self.Code + 1)
mc.makeRead(1, 1, self.Pref + 0x00003000, 3, self.Code + 2)
md.makeRead(1, 1, self.Pref + 0x00004000, 3, self.Code + 3)
self.Code += 4
drv = driverMonitor('tb', Monitors)
seq = sequenceClass.sequenceClass('tb', Monitors, '', [('ma', ma), ('mb', mb),
('mc', mc), ('md', md),
('drv', drv)])
seq.msgCode = 100
def negedge():
global cycles
cycles += 1
veri.force('tb.cycles', str(cycles))
if (cycles > GIVEUP_TIMEOUT):
logs.log_info('finishing on default guard of %d' % GIVEUP_TIMEOUT)
veri.finish()
rst_n = veri.peek('tb.rst_n')
if (rst_n != '1'):
return
'/Library/Frameworks/Python.framework/Versions/3.9/lib/python3.9',
'/Library/Frameworks/Python.framework/Versions/3.9/lib/python3.9/lib-dynload',
'/Users/ilia/Library/Python/3.9/lib/python/site-packages',
'/Users/ilia/Library/Python/3.9/lib/python/site-packages/pyglet-2.0.dev0-py3.9.egg',
'/Library/Frameworks/Python.framework/Versions/3.9/lib/python3.9/site-packages'
]
NewName = os.path.expanduser('~')
sys.path.append('%s/verification_libs3' % NewName)
import logs
Monitors = []
cycles = 0
GIVEUP_TIMEOUT = 1000 # how many cycles to run before retirment.
import sequenceClass
seq = sequenceClass.sequenceClass('tb', Monitors, '', [])
import colorlib
def sequence(TestName):
Seq = logs.bin2string(TestName)
seq.readfile(Seq)
logs.setVar('sequence', Seq)
Dir = os.path.dirname(Seq)
logs.setVar('testsdir', Dir)
logs.log_info('SEQUENCE %d' % len(seq.Sequence))
class driverMonitor(logs.driverClass):
def __init__(self, Path, Monitors):
self.Addresses = []
for X in wrds[1:]:
self.Addresses.append(eval(X))
logs.log_info('ADDRESSES %s' % (list(map(hex, self.Addresses))))
else:
logs.log_error('ACTION unrecognized "%s" ' % Txt)
def onFinish(self):
counts.snapshot()
drv = driverMonitor('tb', Monitors)
seq = sequenceClass.sequenceClass('tb', Monitors, '', [('drv', drv),
('mst0', msts[0]),
('mst1', msts[1]),
('mst2', msts[2]),
('mst3', msts[3])])
seq.msgCode = 100
def negedge():
global cycles
cycles += 1
veri.force('tb.cycles', str(cycles))
if (cycles > GIVEUP_TIMEOUT):
logs.log_info('finishing on default guard of %d' % GIVEUP_TIMEOUT)
veri.finish()
rst_n = veri.peek('tb.rst_n')
if (rst_n != '1'):
return
import os, sys, string, random
import veri
NewName = os.path.expanduser('~')
sys.path.append('%s/verification_libs3' % NewName)
import logs
Monitors = []
cycles = 0
GIVEUP_TIMEOUT = 1000 # how many cycles to run before retirment.
import axiMaster
mst = axiMaster.axiMasterClass('tb', Monitors)
import sequenceClass
seq = sequenceClass.sequenceClass('tb', Monitors, '', [('mst', mst)])
def pymonname(Name):
logs.pymonname(Name)
def sequence(TestName):
Seq = logs.bin2string(TestName)
seq.readfile(Seq)
logs.setVar('sequence', Seq)
Dir = os.path.dirname(Seq)
logs.setVar('testsdir', Dir)
logs.log_info('SEQUENCE %d' % len(seq.Sequence))
def cannot_find_sig(Sig):
slvs = [0,0,0,0]
II = 0
slvs[0] = slvs.append(axiSlave.axiSlaveClass('tb',Monitors0,'slv%s_' % II,'','SLV%d' % II))
II = 1
slvs[1] = slvs.append(axiSlave.axiSlaveClass('tb',Monitors1,'slv%s_' % II,'','SLV%d' % II))
II = 2
slvs[2] = slvs.append(axiSlave.axiSlaveClass('tb',Monitors,'slv%s_' % II,'','SLV%d' % II))
II = 3
slvs[2] = slvs.append(axiSlave.axiSlaveClass('tb',Monitors,'slv%s_' % II,'','SLV%d' % II))
mst = axiMaster.axiMasterClass('tb',Monitors,'mst0_','','MST0')
drv.msts = [mst]
seq = sequenceClass.sequenceClass('tb',Monitors,'',[('drv',drv),('mst0',mst)])
def pymonname(Name):
logs.pymonname(Name)
def sequence(TestName):
Seq = logs.bin2string(TestName)
seq.readfile(Seq)
logs.setVar('sequence',Seq)
Dir = os.path.dirname(Seq)
logs.setVar('testsdir',Dir)
logs.log_info('SEQUENCE %d'%len(seq.Sequence))