def adjust_vd_rs1_rs2_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) reg_count = 1 if 'SEG' in aInstruction.name: layout_opr = aInstruction.find_operand('custom') reg_count = int(layout_opr.regCount) operand_adjustor.set_vd_ls_dest() operand_adjustor.set_rs1_int_ls_base() operand_adjustor.set_rs2_int_ls_base() width = get_element_size(aInstruction.find_operand('const_bits')) attr_dict = dict() subop_dict = dict() subop_dict['base'] = 'rs1' subop_dict['index'] = 'rs2' attr_dict['alignment'] = width attr_dict['base'] = 'rs1' attr_dict['data-size'] = width * reg_count attr_dict['element-size'] = width attr_dict['mem-access'] = 'Read' add_addressing_operand(aInstruction, None, 'LoadStore', 'VectorStridedLoadStoreOperand', subop_dict, attr_dict) operand_adjustor.set_vm() return True
def adjust_rs1_vs2_vd_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_rs1_int_ls_base() operand_adjustor.set_vs2() operand_adjustor.set_vs2_differ_vd() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" subop_dict["index"] = "vs2" attr_dict["base"] = "rs1" attr_dict["mem-access"] = "ReadWrite" add_addressing_operand( aInstruction, None, "LoadStore", "VectorIndexedLoadStoreOperandRISCV", subop_dict, attr_dict, ) operand_adjustor.set_vd_ls_indexed_dest() operand_adjustor.set_vm() return True
def adjust_vd_rs1_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) if aInstruction.iclass == 'VectorLoadStoreInstruction': operand_adjustor.set_vd_ls_dest() operand_adjustor.set_rs1_int_ls_base() width = get_element_size(aInstruction.find_operand('const_bits')) attr_dict = dict() subop_dict = dict() subop_dict['base'] = 'rs1' attr_dict['alignment'] = width attr_dict['base'] = 'rs1' attr_dict['data-size'] = width attr_dict['element-size'] = width attr_dict['mem-access'] = 'Read' add_addressing_operand(aInstruction, None, 'LoadStore', 'VectorBaseOffsetLoadStoreOperand', subop_dict, attr_dict) else: funct3 = aInstruction.find_operand('const_bits').value[11:14] operand_adjustor.set_vd() if funct3 == '101': #OPFVF operand_adjustor.set_rs1_sp() else: operand_adjustor.set_rs1_int() operand_adjustor.set_vm() return True
def adjust_vd_rs1_rs2_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) reg_count = 1 if "SEG" in aInstruction.name: layout_opr = aInstruction.find_operand("custom") reg_count = int(layout_opr.regCount) operand_adjustor.set_vd_ls_dest() operand_adjustor.set_rs1_int_ls_base() operand_adjustor.set_rs2_int_ls_base() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" subop_dict["index"] = "rs2" attr_dict["alignment"] = width attr_dict["base"] = "rs1" attr_dict["data-size"] = width * reg_count attr_dict["element-size"] = width attr_dict["mem-access"] = "Read" add_addressing_operand( aInstruction, None, "LoadStore", "VectorStridedLoadStoreOperandRISCV", subop_dict, attr_dict, ) operand_adjustor.set_vm() return True
def adjust_vd_rs1_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) if aInstruction.iclass == "VectorLoadStoreInstruction": operand_adjustor.set_vd_ls_dest() operand_adjustor.set_rs1_int_ls_base() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" attr_dict["alignment"] = width attr_dict["base"] = "rs1" attr_dict["data-size"] = width attr_dict["element-size"] = width attr_dict["mem-access"] = "Read" add_addressing_operand( aInstruction, None, "LoadStore", "VectorBaseOffsetLoadStoreOperand", subop_dict, attr_dict, ) else: funct3 = aInstruction.find_operand("const_bits").value[11:14] operand_adjustor.set_vd() if funct3 == "101": # OPFVF operand_adjustor.set_rs1_sp() else: operand_adjustor.set_rs1_int() operand_adjustor.set_vm() return True
def adjust_vs3_rs1_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_vs3_ls_source() operand_adjustor.set_rs1_int_ls_base() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" attr_dict["alignment"] = width attr_dict["base"] = "rs1" attr_dict["data-size"] = width attr_dict["element-size"] = width attr_dict["mem-access"] = "Write" add_addressing_operand( aInstruction, None, "LoadStore", "VectorBaseOffsetLoadStoreOperand", subop_dict, attr_dict, ) operand_adjustor.set_vm() return True
def adjust_vd_rs1(aInstruction): if aInstruction.iclass == "LoadStoreInstruction": operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_vd() operand_adjustor.set_rs1_int_ls_base() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" attr_dict["alignment"] = width attr_dict["base"] = "rs1" attr_dict["element-size"] = width attr_dict["mem-access"] = "Read" add_addressing_operand( aInstruction, None, "LoadStore", "VectorBaseOffsetLoadStoreOperandRISCV", subop_dict, attr_dict, ) else: operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_vd() if ".F" in aInstruction.name: operand_adjustor.set_rs1_sp() else: operand_adjustor.set_rs1_int() return True
def adjust_vs3_rs1(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_vs3_ls_source() operand_adjustor.set_rs1_int_ls_base() width = get_element_size(aInstruction.find_operand('const_bits')) attr_dict = dict() subop_dict = dict() subop_dict['base'] = 'rs1' attr_dict['alignment'] = width attr_dict['base'] = 'rs1' attr_dict['data-size'] = width attr_dict['element-size'] = width attr_dict['mem-access'] = 'Write' add_addressing_operand(aInstruction, None, 'LoadStore', 'VectorBaseOffsetLoadStoreOperand', subop_dict, attr_dict) return True
def adjust_rs1_vs2_vd_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_rs1_int_ls_base() operand_adjustor.set_vs2() operand_adjustor.set_vs2_differ_vd() width = get_element_size(aInstruction.find_operand('const_bits')) attr_dict = dict() subop_dict = dict() subop_dict['base'] = 'rs1' subop_dict['index'] = 'vs2' attr_dict['base'] = 'rs1' attr_dict['mem-access'] = 'ReadWrite' add_addressing_operand(aInstruction, None, 'LoadStore', 'VectorIndexedLoadStoreOperandRISCV', subop_dict, attr_dict) operand_adjustor.set_vd_ls_indexed_dest() operand_adjustor.set_vm() return True