def x_read(self, time, signal):
okeq(self._state, 'active')
self._state = 'reading'
# Note: does not block until
# output, but do have a short
# delay before clr is valid.
index = min(self._addr, len(self._rom) - 1)
data = self._rom[index]
self.seq.addall([(time + self._t_delay,
Action(self, '_output_update', data)),
(time + self._t_rd2clr, Action(self, '_read_done'))])
def x_read(self, time, signal):
"""
Address enable input.
Event triggered.
"""
okeq(self._state, 'idle')
self._state = 'reading'
value = self._ram_content.get(self._addr, 0)
self._ram_content[self._addr] = 0
self.seq.addall([(time + self._t_r2wc, Action(self, '_read_done')),
(time + self._t_delay,
Action(self, '_output_update', value))])
def d_in(self, time, signal):
okeq(self._state, 'read-but-not-written')
self._state = 'writing'
self.seq.add((time + self._t_w2c, Action(self, '_write_done')))
value = signal.state
okeq(isinstance(value, (int, float)), True)
self._ram_content[self._addr] = int(value)
def _do_phase(self, time):
i_this_phase = self.i_next_phase
self.i_next_phase = (self.i_next_phase + 1) % self.n_phases
phase_name = self.phase_names_and_default_durations[i_this_phase][0]
phase_duration = self.phase_durations[i_this_phase]
self.current_phase.set(time, phase_name)
getattr(self, phase_name).set(time, '!')
return (time + phase_duration, Action(self, '_do_phase'))
def x_asel(self, time, signal):
"""
Address enable input.
Event triggered.
"""
okeq(self._state, 'idle')
self._state = 'enabling-address'
self.seq.add((time + self._t_sel2rd, Action(self, '_a_enabled')))
def input(self, time, signal):
state = signal.state
if state != signal.previous:
# output ok till change?
# self.output.set(SIG_UNDEF)
self.seq.add((
time + self.delay,
Action(self,
'_set_delay',
signal.state)))
def _input_event(self, i_in, time, state):
if self._state == 'idle':
self._state = 'get-updates'
self._time = time
if self.pass_all_events:
# just do it now
self._update_output(time)
else:
# schedule an update after
# all 'normal' events
# at this timepoint.
self.seq.add(((time, -9999), Action(self, '_update_output')))
else:
okeq(self._state, 'get-updates')
okeq(time, self._time)
def start(self, time, signal):
self.seq.add((time, Action(self, '_do_phase')))
def in2(self, t, sig):
self._in[1] = sig.state
self._changes[1] = 1
self.out.set(t, SIG_UNDEF)
self.seq.add((t + self._settle, Action(self, '_done', 1)))
def x_aclr(self, time, signal):
okeq(self._state, 'active')
self._state = 'disabling-address'
self.seq.add((time + self._t_clr2ad, Action(self, '_a_cleared')))
def addr(self, time, signal):
"""Address input."""
okeq(self._state, 'idle')
self._state = 'set-addr'
self._addr = signal.state
self.seq.add((time + self._t_a2sel, Action(self, '_a_changed')))
def x_aclr(self, time, signal):
okin(self._state, ('read-but-not-written', 'read-and-written'))
self._state = 'disabling-address'
self.seq.add((time + self._t_c2a, Action(self, '_a_cleared')))