def barrier():
for i in range(NUM_PORTS):
simLib.fPort(i + 1).write("%08d"%CMD_BARRIER + " // BARRIER\n")
simLib.fPort(i + 1).write("%08x"%(numExpectedPktsPHY[i]) +
" // Number of Packets\n")
simLib.fPCI().write("%08d"%CMD_PCI_BARRIER + " // BARRIER\n")
for i in range(NUM_PORTS):
simLib.fPCI().write("%08x"%(numExpectedPktsDMA[i]) +
" // Number of expected pkts received via DMA port " +
str(i + 1) + "\n")
resetBarrier()
def barrier():
for i in range(NUM_PORTS):
simLib.fPort(i + 1).write("%08d"%CMD_BARRIER + " // BARRIER\n")
simLib.fPort(i + 1).write("%08x"%(numExpectedPktsPHY[i]) +
" // Number of Packets\n")
simLib.fPCI().write("%08d"%CMD_PCI_BARRIER + " // BARRIER\n")
for i in range(NUM_PORTS):
simLib.fPCI().write("%08x"%(numExpectedPktsDMA[i]) +
" // Number of expected pkts received via DMA port " +
str(i + 1) + "\n")
resetBarrier()
def regDMA(queue, length):
f = simLib.fPCI()
f.write("// DMA: QUEUE: " + hex(queue) + " LENGTH: " + hex(length) + "\n")
f.write("00000003 // DMA\n")
f.write("%08x" % queue + " // Queue (" + hex(queue) + ")\n")
f.write("%08x" % length + " // Length (" + hex(length) + ")\n")
f.write("00000000" + " // Mask (0x0)\n")
def regDMA(queue, length):
f = simLib.fPCI()
f.write("// DMA: QUEUE: "+hex(queue)+ " LENGTH: "+hex(length)+"\n")
f.write("00000003 // DMA\n")
f.write("%08x"%queue +" // Queue ("+hex(queue)+")\n")
f.write("%08x"%length+" // Length ("+hex(length)+")\n")
f.write("00000000"+" // Mask (0x0)\n")
def regWrite(reg, value):
f = simLib.fPCI()
f.write("// WRITE: Address: " + hex(reg) + " Data: " + hex(value) + "\n")
f.write("00000002" + " // WRITE\n")
f.write("%08x" % reg + " // Address \n")
f.write("%08x" % value + " // Data (" + hex(value) + ")\n")
f.write("00000000" + " // Mask (0x0)\n")
def regWrite(reg, value):
f = simLib.fPCI()
f.write("// WRITE: Address: "+hex(reg)+" Data: "+hex(value)+"\n")
f.write("00000002"+" // WRITE\n")
f.write("%08x"%reg + " // Address \n")
f.write("%08x"%value+" // Data ("+hex(value)+")\n")
f.write("00000000"+" // Mask (0x0)\n")
def regRead(reg, value):
f = simLib.fPCI()
f.write("// READ: Address: "+hex(reg)+" Expected Data: "+hex(value)+"\n")
f.write("00000001 // READ\n")
f.write("%08x"%reg+" // Address ("+hex(reg)+")\n")
f.write("%08x"%value+" // Data ("+hex(value)+")\n")
f.write("FFFFFFFF"+" // Mask (0xFFFFFFFF)\n")
def regRead(reg, value):
f = simLib.fPCI()
f.write("// READ: Address: " + hex(reg) + " Expected Data: " +
hex(value) + "\n")
f.write("00000001 // READ\n")
f.write("%08x" % reg + " // Address (" + hex(reg) + ")\n")
f.write("%08x" % value + " // Data (" + hex(value) + ")\n")
f.write("FFFFFFFF" + " // Mask (0xFFFFFFFF)\n")
def delay(nanoSeconds):
for i in range(NUM_PORTS):
simLib.fPort(i+1).write("%08d"%CMD_DELAY + " // DELAY\n")
simLib.fPort(i+1).write("%08x"%(MSB_MASK & nanoSeconds) +
" // Delay (MSB) " + str(nanoSeconds)+" ns\n")
simLib.fPort(i+1).write("%08x"%(MSB_MASK & nanoSeconds) +
" // Delay (LSB) " + str(nanoSeconds)+" ns\n")
simLib.fPCI().write("%08d"%CMD_PCI_DELAY+" // DELAY\n")
simLib.fPCI().write("%08x"%(MSB_MASK & nanoSeconds) + " // Delay (MSB) " +
str(nanoSeconds) + " ns\n")
simLib.fPCI().write("%08x"%(LSB_MASK & nanoSeconds) + " // Delay (LSB) " +
str(nanoSeconds) + " ns\n")
def delay(nanoSeconds):
for i in range(NUM_PORTS):
simLib.fPort(i+1).write("%08d"%CMD_DELAY + " // DELAY\n")
simLib.fPort(i+1).write("%08x"%(MSB_MASK & nanoSeconds) +
" // Delay (MSB) " + str(nanoSeconds)+" ns\n")
simLib.fPort(i+1).write("%08x"%(MSB_MASK & nanoSeconds) +
" // Delay (LSB) " + str(nanoSeconds)+" ns\n")
simLib.fPCI().write("%08d"%CMD_PCI_DELAY+" // DELAY\n")
simLib.fPCI().write("%08x"%(MSB_MASK & nanoSeconds) + " // Delay (MSB) " +
str(nanoSeconds) + " ns\n")
simLib.fPCI().write("%08x"%(LSB_MASK & nanoSeconds) + " // Delay (LSB) " +
str(nanoSeconds) + " ns\n")
def regDelay(nanoSeconds):
simLib.fPCI().write("00000005 // DELAY \n")
simLib.fPCI().write("%08x" % (MSB_MASK & nanoSeconds) +
" // Delay (MSB) " + str(nanoSeconds) + " ns\n")
simLib.fPCI().write("%08x" % (LSB_MASK & nanoSeconds) +
" // Delay (LSB) " + str(nanoSeconds) + " ns\n")
def regDelay(nanoSeconds):
simLib.fPCI().write("00000005 // DELAY \n")
simLib.fPCI().write("%08x"%(MSB_MASK & nanoSeconds) + " // Delay (MSB) "
+ str(nanoSeconds) + " ns\n")
simLib.fPCI().write("%08x"%(LSB_MASK & nanoSeconds) + " // Delay (LSB) "
+ str(nanoSeconds) + " ns\n")
