def regWrite(reg, value):
f = simLib.fregstim()
f.write("# WRITE\n")
f.write("W " + "%08x\n"%CMD_WRITE)
f.write("%08x, "%reg) # // Address
f.write("%08x, "%value) # // Data
f.write("f, -.\n")
g = simLib.fregexpect()
g.write("# WRITE\n")
g.write("W " + "%08x\n"%CMD_WRITE)
g.write("%08x, "%reg) # // Address
g.write("%08x, "%value) # // Data
g.write("f, -.\n")
def regWrite(reg, value):
f = simLib.fregstim()
f.write("# WRITE\n")
f.write("W " + "%08x\n" % CMD_WRITE)
f.write("%08x, " % reg) # // Address
f.write("%08x, " % value) # // Data
f.write("f, -.\n")
g = simLib.fregexpect()
g.write("# WRITE\n")
g.write("W " + "%08x\n" % CMD_WRITE)
g.write("%08x, " % reg) # // Address
g.write("%08x, " % value) # // Data
g.write("f, -.\n")
def regRead(reg, val):
f = simLib.fregexpect()
simLib.fregexpect().write("# READ\n")
f.write("R " + "%08x\n" % CMD_READ) # // READ
f.write("%08x, " % reg) # // Address
f.write("%08x.\n" % val) # // Data
def regRead(reg, val):
f = simLib.fregexpect()
simLib.fregexpect().write("# READ\n")
f.write("R " + "%08x\n"%CMD_READ) # // READ
f.write("%08x, "%reg) # // Address
f.write("%08x.\n"%val) # // Data
