def test_write_registers_are_not_checked_in_units_without_write_lock(self):
"""Test opportune write register access check.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(
ICaseString(name), 1, ["ALU"], LockInfo(rd_lock, wr_lock),
[]) for name, rd_lock, wr_lock in [("input", False,
False), ("output", True,
True)])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [in_unit])],
[], [])
self.assertEqual(
simulate([
HwInstruction(*instr_regs, "ALU")
for instr_regs in [[["R1"], "R2"], [[], "R1"]]
], HwSpec(proc_desc)), [
BagValDict(cp_util) for cp_util in [{
ICaseString("input"): [InstrState(0)]
}, {
ICaseString("input"): [InstrState(1)],
ICaseString("output"): [InstrState(0)]
}, {
ICaseString("output"): [InstrState(1)]
}]
])
def test_instructions_flow_seamlessly(self):
"""Test instructions are moved successfully along the pipeline.
`self` is this test case.
"""
big_input, small_input1, mid1, small_input2, mid2, out_unit = (
UnitModel(ICaseString(name), width, ["ALU"], LockInfo(
rd_lock, wr_lock), []) for name, width, rd_lock, wr_lock in
[("big input", 4, True, False), ("small input 1", 1, True, False),
("middle 1", 1, False, False), ("small input 2", 1, True, False),
("middle 2", 2, False, False), ("output", 2, False, True)])
proc_desc = ProcessorDesc([big_input, small_input1, small_input2], [
FuncUnit(out_unit, [big_input, mid2])], [], starmap(FuncUnit, [
[mid2, [mid1, small_input2]], [mid1, [small_input1]]]))
self.assertEqual(simulate(
[HwInstruction([], out_reg, "ALU") for out_reg in
["R1", "R2", "R3", "R4", "R5", "R6"]],
HwSpec(proc_desc)), [BagValDict(cp_util) for cp_util in [
{ICaseString("big input"): map(InstrState, [0, 1, 2, 3]),
ICaseString("small input 1"): [InstrState(4)],
ICaseString("small input 2"): [InstrState(5)]},
{ICaseString("big input"): (InstrState(
instr, StallState.STRUCTURAL) for instr in [2, 3]),
ICaseString("output"): map(InstrState, [0, 1]),
ICaseString("middle 1"): [InstrState(4)],
ICaseString("middle 2"): [InstrState(5)]},
{ICaseString("output"): map(InstrState, [2, 3]),
ICaseString("middle 2"):
starmap(InstrState, [[5, StallState.STRUCTURAL], [4]])},
{ICaseString("output"): map(InstrState, [4, 5])}]])
def test_hazard(self):
"""Test structural hazards in a unified memory architecture.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(
ICaseString(name), 1, ["ALU", "MEM"], LockInfo(rd_lock, wr_lock),
mem_acl) for name, rd_lock, wr_lock, mem_acl in [(
"input", True, False,
["ALU", "MEM"]), ("output", False, True, ["MEM"])])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [in_unit])],
[], [])
self.assertEqual(
simulate([
HwInstruction([], out_reg, "ALU") for out_reg in ["R1", "R2"]
], HwSpec(proc_desc)), [
BagValDict(cp_util) for cp_util in [{
ICaseString("input"): [InstrState(0)]
}, {
ICaseString("output"): [InstrState(0)],
ICaseString("input"): [InstrState(1)]
}, {
ICaseString("output"): [InstrState(1)]
}]
])
def test_all_candidate_instructions_are_offered_to_the_destinaton_unit(
self):
"""Test candidate instructions aren't shortlisted.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(ICaseString(name), width,
["ALU", "MEM"],
LockInfo(rd_lock, wr_lock), mem_acl)
for name, width, rd_lock, wr_lock, mem_acl in [(
"input", 3, True, False,
[]), ("output", 2, False, True, ["MEM"])])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [in_unit])],
[], [])
self.assertEqual(
simulate([
HwInstruction([], *instr_params) for instr_params in
[["R1", "MEM"], ["R2", "MEM"], ["R3", "ALU"]]
], HwSpec(proc_desc)), [
BagValDict(cp_util) for cp_util in [{
ICaseString("input"):
map(InstrState, [0, 1, 2])
}, {
ICaseString("output"):
map(InstrState, [0, 2]),
ICaseString("input"):
[InstrState(1, StallState.STRUCTURAL)]
}, {
ICaseString("output"): [InstrState(1)]
}]
])
def test_mem_ACL_is_correctly_matched_against_instructions(self):
"""Test comparing memory ACL against instructions.
`self` is this test case.
"""
res_util = (BagValDict(
{ICaseString("full system"): [InstrState(instr)]})
for instr in [0, 1])
assert simulate(
[
HwInstruction([], out_reg, ICaseString("ALU"))
for out_reg in ["R1", "R2"]
],
HwSpec(
processor_utils.load_proc_desc({
"units": [{
units.UNIT_NAME_KEY: "full system",
units.UNIT_WIDTH_KEY: 2,
units.UNIT_CAPS_KEY: ["ALU"],
**{
attr: True
for attr in [
units.UNIT_RLOCK_KEY, units.UNIT_WLOCK_KEY
]
}, units.UNIT_MEM_KEY: ["ALU"]
}],
"dataPath": []
}))) == list(res_util)
def test_RLock_in_unit_before_WLock(self):
"""Test detecting RAW hazards with read locks in earlier units.
`self` is this test case.
"""
in_unit, mid, out_unit = (UnitModel(ICaseString(name), 1, ["ALU"],
LockInfo(rd_lock, wr_lock), [])
for name, rd_lock, wr_lock in [(
"input", False,
False), ("middle", True,
False), ("output", False,
True)])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [mid])], [],
[FuncUnit(mid, [in_unit])])
self.assertEqual(
simulate([
HwInstruction(*instr_regs, "ALU")
for instr_regs in [[[], "R1"], [["R1"], "R2"]]
], HwSpec(proc_desc)), [
BagValDict(cp_util) for cp_util in [{
ICaseString("input"): [InstrState(0)]
}, {
ICaseString("input"): [InstrState(1)],
ICaseString("middle"): [InstrState(0)]
}, {
ICaseString("middle"): [InstrState(1, StallState.DATA)],
ICaseString("output"): [InstrState(0)]
}, {
ICaseString("middle"): [InstrState(1)]
}, {
ICaseString("output"): [InstrState(1)]
}]
])
def test_sim(self, prog, cpu, util_tbl):
"""Test executing a program.
`self` is this test case.
`prog` is the program to run.
`cpu` is the processor to run the program on.
`util_tbl` is the expected utilization table.
"""
assert simulate([HwInstruction(*regs, ICaseString(categ)) for
*regs, categ in prog], HwSpec(cpu)) == [
BagValDict(inst_util) for inst_util in util_tbl]
def test_processor(self, prog_file, proc_file, util_info):
"""Test simulating a program on the given processor.
`self` is this test case.
`prog_file` is the program file.
`proc_file` is the processor description file.
`util_info` is the expected utilization information.
"""
cpu = read_proc_file("processors", proc_file)
capabilities = processor_utils.get_abilities(cpu)
assert simulate(test_utils.compile_prog(
prog_file, test_utils.read_isa_file(
"singleInstructionISA.yaml", capabilities)), HwSpec(cpu)) == [
BagValDict(inst_util) for inst_util in util_info]
def test_mem_util_in_earlier_inputs_affects_later_ones(self):
"""Test propagation of memory utilization among inputs.
`self` is this test case.
"""
full_sys_unit = UnitModel(ICaseString("full system"), 2, ["ALU"],
LockInfo(True, True), ["ALU"])
res_util = (BagValDict(
{ICaseString("full system"): [InstrState(instr)]})
for instr in [0, 1])
assert simulate(
[HwInstruction([], out_reg, "ALU") for out_reg in ["R1", "R2"]],
HwSpec(ProcessorDesc([], [], [full_sys_unit],
[]))) == list(res_util)
def test_util_tbl_exists_in_StallError(self):
"""Test dumping the utilizaiton table in stall errors.
`self` is this test case.
"""
long_input, mid, short_input, out_unit = (
UnitModel(ICaseString(name), 1, ["ALU"],
LockInfo(rd_lock, wr_lock), []) for name, rd_lock,
wr_lock in [("long input", False, False), ("middle", False, False),
("short input", False, False), ("output", True, True)])
proc_desc = ProcessorDesc([long_input, short_input], [FuncUnit(
out_unit, [mid, short_input])], [], [FuncUnit(mid, [long_input])])
with self.assertRaises(StallError) as ex_chk:
simulate([HwInstruction(*instr_regs, "ALU") for instr_regs in
[[[], "R1"], [["R1"], "R2"]]], HwSpec(proc_desc))
self.assertEqual(ex_chk.exception.processor_state, [
BagValDict(cp_util) for cp_util in
[{ICaseString("long input"): [InstrState(0)], ICaseString(
"short input"): [InstrState(1)]},
{ICaseString("middle"): [InstrState(0)], ICaseString("output"):
[InstrState(1, StallState.DATA)]},
{ICaseString("middle"): [InstrState(0, StallState.STRUCTURAL)],
ICaseString("output"): [InstrState(1, StallState.DATA)]}]])
def test_hazard(self):
"""Test detecting RAR hazards.
`self` is this test case.
"""
proc_desc = ProcessorDesc([], [], [
UnitModel(ICaseString(TEST_DIR), 2, ["ALU"], LockInfo(True, True),
[])
], [])
self.assertEqual(
simulate([
HwInstruction(["R1"], out_reg, "ALU")
for out_reg in ["R2", "R3"]
], HwSpec(proc_desc)),
[BagValDict({ICaseString(TEST_DIR): map(InstrState, [0, 1])})])
def get_sim_res(processor_file: IO[str],
program_file: Iterable[str]) -> List[List[str]]:
"""Calculate the simulation result table.
`processor_file` is the file containing the processor architecture.
`program_file` is the file containing the program to simulate.
The function reads the program file and simulates its execution on
the processor defined by the architecture provided in the given
processor description file.
"""
proc_desc = hw_loading.read_processor(processor_file)
prog = program_utils.read_program(program_file)
compiled_prog = program_utils.compile_program(prog, proc_desc.isa)
proc_spec = sim_services.HwSpec(proc_desc.processor)
return _get_sim_rows(
enumerate(sim_services.simulate(compiled_prog, proc_spec)), len(prog))
def test_instructions_are_loaded_to_lexicographically_inputs_first(self):
"""Test instructions are fed into sorted input units.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(ICaseString(name), 1, ["ALU"], LockInfo(
rd_lock, wr_lock), mem_acl) for name, rd_lock, wr_lock, mem_acl in
[("input 1", True, False, []),
("output 1", False, True, ["ALU"])])
proc_desc = ProcessorDesc(
[in_unit], [FuncUnit(out_unit, [in_unit])], [UnitModel(ICaseString(
"input 2"), 1, ["ALU"], LockInfo(True, False), [])], [])
self.assertEqual(simulate(
[HwInstruction([], "R1", "ALU")], HwSpec(proc_desc)), [BagValDict(
cp_util) for cp_util in [{ICaseString("input 1"): [InstrState(
0)]}, {ICaseString("output 1"): [InstrState(0)]}]])
def test_hazard(self, instr_regs):
"""Test detecting data hazards.
`self` is this test case.
`instr_regs` are the registers accessed by each instruction.
"""
full_sys_unit = UnitModel(ICaseString(TEST_DIR), 2, ["ALU"],
LockInfo(True, True), [])
assert simulate(
[HwInstruction(*regs, "ALU") for regs in instr_regs],
HwSpec(ProcessorDesc([], [], [full_sys_unit], []))) == [
BagValDict(cp_util) for cp_util in [{
ICaseString(TEST_DIR):
itertools.starmap(InstrState, [[0], [1, StallState.DATA]])
}, {
ICaseString(TEST_DIR): [InstrState(1)]
}]
]
def test_only_mem_access_instructions_are_checked(self):
"""Test always allowing instructions without memory access.
`self` is this test case.
"""
in_unit, out_unit = (UnitModel(ICaseString(name), 2, ["ALU", "MEM"],
LockInfo(rd_lock, wr_lock), mem_acl)
for name, rd_lock, wr_lock, mem_acl in [(
"input", True, False,
[]), ("output", False, True, ["MEM"])])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [in_unit])],
[], [])
self.assertEqual(
simulate([
HwInstruction([], *instr_params)
for instr_params in [["R1", "MEM"], ["R2", "ALU"]]
], HwSpec(proc_desc)), [
BagValDict({ICaseString(unit): map(InstrState, [0, 1])})
for unit in ["input", "output"]
])
def test_internal_stall_is_detected(self):
"""Test detecting stalls in internal units.
`self` is this test case.
"""
in_unit, mid, out_unit = (
UnitModel(ICaseString(name), width, ["ALU"],
LockInfo(rd_lock, wr_lock), []) for
name, width, rd_lock, wr_lock in [("input", 2, True, False), (
"middle", 2, False, False), ("output", 1, False, True)])
proc_desc = ProcessorDesc([in_unit], [FuncUnit(out_unit, [mid])], [],
[FuncUnit(mid, [in_unit])])
self.assertEqual(simulate(
[HwInstruction([], out_reg, "ALU") for out_reg in ["R1", "R2"]],
HwSpec(proc_desc)), [BagValDict(cp_util) for cp_util in [
{ICaseString("input"): map(InstrState, [0, 1])},
{ICaseString("middle"): map(InstrState, [0, 1])},
{ICaseString("middle"): [InstrState(1, StallState.STRUCTURAL)],
ICaseString("output"): [InstrState(0)]},
{ICaseString("output"): [InstrState(1)]}]])
def test_earlier_instructions_are_propagated_first(self):
"""Test earlier instructions are selected first.
`self` is this test case.
"""
in_units = [UnitModel(
ICaseString(name), 1, [categ], LockInfo(True, False), []) for name,
categ in [("ALU input", "ALU"), ("MEM input", "MEM")]]
out_unit = UnitModel(ICaseString("output"), 1, ["ALU", "MEM"],
LockInfo(False, True), [])
proc_desc = ProcessorDesc(
in_units, [FuncUnit(out_unit, in_units)], [], [])
self.assertEqual(simulate([HwInstruction(
*instr_params) for instr_params in [[[], "R12", "MEM"], [
["R11", "R15"], "R14", "ALU"]]], HwSpec(proc_desc)), [
BagValDict(inst_util) for inst_util in
[{ICaseString("MEM input"): [InstrState(0)],
ICaseString("ALU input"): [InstrState(1)]},
{ICaseString("output"): [InstrState(0)], ICaseString(
"ALU input"): [InstrState(1, StallState.STRUCTURAL)]},
{ICaseString("output"): [InstrState(1)]}]])
def test_stalled_outputs_are_not_flushed(self, extra_instr_lst):
"""Test data hazards at output ports.
`self` is this test case.
`extra_instr_lst` is the extra instructions to execute after the
ones causing the hazard.
"""
program = starmap(HwInstruction, chain(
[[[], "R1", "ALU"], [["R1"], "R2", "ALU"]], extra_instr_lst))
extra_instr_len = len(extra_instr_lst)
cores = starmap(lambda name, width: UnitModel(
ICaseString(name), width, ["ALU"], LockInfo(True, True), []),
[("core 1", 1), ("core 2", 1 + extra_instr_len)])
extra_instr_seq = range(2, 2 + extra_instr_len)
assert simulate(
tuple(program), HwSpec(ProcessorDesc([], [], cores, []))) == [
BagValDict(cp_util) for cp_util in
[{ICaseString("core 1"): [InstrState(0)], ICaseString(
"core 2"): starmap(InstrState, more_itertools.prepend(
[1, StallState.DATA],
([instr] for instr in extra_instr_seq)))},
{ICaseString("core 2"): [InstrState(1)]}]]
def test_hazard(self, in_width, in_mem_util, out_unit_params, extra_util):
"""Test detecting structural hazards.
`self` is this test case.
`in_width` is the width of the input unit.
`in_mem_util` is the list of input unit capabilities requiring
memory utilization.
`out_unit_params` are the creation parameters of output units.
`extra_util` is the extra utilization beyond the second clock
pulse.
"""
in_unit = UnitModel(ICaseString("input"), in_width, ["ALU"],
LockInfo(True, False), in_mem_util)
out_units = (UnitModel(ICaseString(name), width, ["ALU"],
LockInfo(False, True), mem_access)
for name, width, mem_access in out_unit_params)
out_units = (FuncUnit(out_unit, [in_unit]) for out_unit in out_units)
cp1_util = {ICaseString("input"): map(InstrState, range(in_width))}
assert simulate(
[HwInstruction([], out_reg, "ALU") for out_reg in ["R1", "R2"]],
HwSpec(ProcessorDesc([in_unit], out_units, [], []))) == list(
map(BagValDict, more_itertools.prepend(cp1_util, extra_util)))