def load_system(file_path): sys, prop = loadsystem.parse(file_path) sys.init_sims(plt_lib=None, psim_args=None) # useful to talk about the parameterization of ci without talking about # delta_t prop.delta_t = sys.delta_t #step_sim = simsys.get_step_simulator( # sys.controller_sim, # sys.plant_sim, # sys.delta_t) #trace = sim(py_x, t0, tf, py_u, pvt); #system_sim = simsys.get_system_simulator(step_sim, sys.delta_t, sys.num_dims) system_sim = simsys.get_system_simulator(sys) # simstate encapsulates pvt, s, d, def one_shot_sim(x, t0, tf, w, simstate=None): if t0 != 0: raise err.Fatal('t0 must be 0!') else: # TODO: construct numpy arrays in loadsystem # This will require changing code into quite afew # places...carefull! s = np.array(prop.initial_controller_state) d = np.array(prop.initial_discrete_state) pvt = np.zeros(1) ci_array = w return system_sim(x, s, d, pvt, t0, tf, ci_array) return one_shot_sim, prop
def simulate(sys, prop, opts): num_samples = opts.num_sim_samples num_violations = 0 concrete_states = sample.sample_init_UR(sys, prop, num_samples) trace_list = [] sys_sim = simsys.get_system_simulator(sys) for i in tqdm.trange(num_samples): trace = simsys.simulate(sys_sim, concrete_states[i], prop.T) trace_list.append(trace) sat_x, sat_t = check_prop_violation(trace, prop) if sat_x.size != 0: num_violations += 1 print('x0={} -> x={}, t={}...num_vio_counter={}'.format( trace.x_array[0, :], sat_x[0, :], # the first violating state sat_t[0], # corresponding time instant num_violations), file=SYS.stderr) print('number of violations: {}'.format(num_violations)) return trace_list
def simulate(sys, prop, opts): num_samples = opts.num_sim_samples num_violations = 0 concrete_states = sample.sample_init_UR(sys, prop, num_samples) trace_list = [] sys_sim = simsys.get_system_simulator(sys) for i in tqdm.trange(num_samples): trace = simsys.simulate(sys_sim, concrete_states[i], prop.T) trace_list.append(trace) sat_x, sat_t = check_prop_violation(trace, prop) if sat_x.size != 0: num_violations += 1 print( 'x0={} -> x={}, t={}...num_vio_counter={}'.format( trace.x_array[0, :], sat_x[0, :], # the first violating state sat_t[0], # corresponding time instant num_violations), file=SYS.stderr) print('number of violations: {}'.format(num_violations)) return trace_list
def falsify(sys, prop, opts, current_abs, sampler): # sys controller_sim = sys.controller_sim plant_sim = sys.plant_sim # prop init_cons_list = prop.init_cons_list init_cons = prop.init_cons final_cons = prop.final_cons ci = prop.ci pi = prop.pi initial_discrete_state = prop.initial_discrete_state initial_controller_state = prop.initial_controller_state MAX_ITER = prop.MAX_ITER #TODO: hack to make random_test sample ci_cells when doing # ss-concrete. It is false if ss-symex (and anything else) is # asked for, because then ci_seq consists if concrete values. Can # also be activated for symex as an option, but to be done later. sample_ci = opts.METHOD == 'concrete' or opts.METHOD == 'concrete_no_controller' # options #plot = opts.plot initial_discrete_state = tuple(initial_discrete_state) initial_controller_state = np.array(initial_controller_state) # make a copy of the original initial plant constraints original_plant_cons_list = init_cons_list pi_ref = wmanager.WMap(pi, sys.pi_grid_eps) ci_ref = wmanager.WMap(ci, sys.ci_grid_eps) if sample_ci else None # f1 = plt.figure() ## ## plt.grid(True) ## ## ax = f1.gca() ## eps = current_abs.plant_abs.eps ## #ax.set_xticks(np.arange(0, 2, eps[0])) ## #ax.set_yticks(np.arange(0, 20, eps[1])) ## ## f1.suptitle('abstraction') args = (current_abs, init_cons_list, final_cons, initial_discrete_state, initial_controller_state, plant_sim, controller_sim, ci, pi, sampler, #plot, init_cons, original_plant_cons_list, MAX_ITER, sample_ci, pi_ref, ci_ref, opts) if opts.refine == 'init': refine_init(*args) elif opts.refine == 'trace': refine_trace(*args) elif (opts.refine == 'model-dft' or opts.refine == 'model-rel' or opts.refine == 'model-dmt' or opts.refine == 'model-dct'): sys_sim = simsys.get_system_simulator(sys) falsify_using_model(*args, sys_sim=sys_sim, sys=sys, prop=prop) else: raise err.Fatal('internal')