def test_set_default_packages(self):
"""Prove package selection mechanism works"""
package_manager.set_default_packages(["core"]) # Default of module
components = OrderedDict({
"imm": Bus(24),
"exts": Bus(2),
"imm32": Bus(32)
})
# Expect failure
try:
obj_extender = package_manager.construct("Extender", {
"imm": "imm",
"exts": "exts",
"imm32": "imm32"
}, None, components)
components.update({"extender": obj_extender})
self.assertTrue(False)
except Exception as e:
self.assertTrue(True)
# Expect success
package_manager.set_default_packages(["arm"
]) # Change default packages
obj_extender = package_manager.construct("Extender", {
"imm": "imm",
"exts": "exts",
"imm32": "imm32"
}, None, components)
components.update({"extender": obj_extender})
def test_run(self):
"""
tests the enxtender's run function
"""
imm = Bus(24)
imm32 = Bus(32)
exts = Bus(2)
# initialize extender
e = Extender(imm, exts, imm32)
# initialize input with value 5096
imm.write(0b000000000001001111101000)
# test case 4
exts.write(0)
e.run()
self.assertEqual(imm32.read(), 0xA0000003)
# test case 5
exts.write(1)
e.run()
self.assertEqual(imm32.read(), 0b001111101000)
# test case 6
exts.write(2)
e.run()
self.assertEqual(imm32.read(), 0b100111110100000)
# test case 7
imm.write(0b100000000001001111101000)
e.run()
self.assertEqual(imm32.read(), 0b11111110000000000100111110100000)
def test_modify(self):
"Verifies internal hook modify function"
clk = Bus(1, 0)
rst = Bus(1, 0)
d_bus = Bus(8, 0)
q_bus = Bus(8, 0)
reg = Register(8, clk, rst, d_bus, q_bus, 1)
tm = None
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {}
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {'state': '0'}
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {'state': -1}
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {'state': 256}
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {'state': 128}
rm = reg.modify(tm)
self.assertTrue('success' in rm and rm['success'])
reg.run()
self.assertTrue(q_bus.read() == 128)
def _generate_architecture():
"Generates a valid simple architecture for test"
hooks = OrderedDict([('clk', Clock(1)), ('rst', Reset(0))])
hooks.update({'d_bus': Bus(8, 0)})
hooks.update({'q_bus': Bus(8, 0)})
hooks.update({'const_1': Constant(8, 1)})
entities = OrderedDict([('clk', hooks['clk'])])
entities.update({
'reg':
Register(8,
hooks['clk'],
hooks['rst'],
hooks['d_bus'],
hooks['q_bus'],
default_state=255)
})
hooks.update({'reg': entities['reg']})
entities.update({
'adder':
Adder(8, hooks['q_bus'], hooks['const_1'], hooks['d_bus'])
})
arch = Architecture(0.25, hooks['clk'], hooks['rst'], None, hooks,
entities)
return arch, hooks, entities
def test_constructor(self):
"Constructor with valid and invalid configuration"
c0 = Constant(16, 0xAAAA)
b0 = Bus(4)
b1 = Bus(8)
b2 = Bus(2)
b3 = Bus(2)
with self.assertRaises(TypeError):
bj = BusSubset(None, None, None)
with self.assertRaises(TypeError):
bj = BusSubset('0', None, None)
with self.assertRaises(TypeError):
bj = BusSubset(c0, None, None)
with self.assertRaises(TypeError):
bj = BusSubset(c0, [], [])
with self.assertRaises(ValueError):
bj = BusSubset(c0, ['0'], [(0, 1)])
with self.assertRaises(TypeError):
bj = BusSubset(c0, [b0], [])
with self.assertRaises(TypeError):
bj = BusSubset(c0, [b0], ['0'])
with self.assertRaises(TypeError):
bj = BusSubset(c0, [b0], [('0', '1')])
with self.assertRaises(ValueError):
bj = BusSubset(c0, [b0], [(1, 0)])
with self.assertRaises(ValueError):
bj = BusSubset(c0, [b0], [(0, 1)])
with self.assertRaises(ValueError):
bj = BusSubset(c0, [b0], [(0, 8)])
bs = BusSubset(c0, [b0, b1, b2, b3], [(0, 4), (4, 12), (12, 14),
(14, 16)])
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({
"pc4f": Bus(32),
"pc8f": Bus(32),
"instrf": Bus(32),
"stall": Bus(1),
"flush": Bus(1),
"clk": Bus(1),
"pc4d": Bus(32),
"pc8d": Bus(32),
"instrd": Bus(32),
"enable": Bus(1)
})
config = {
"pc4f": "pc4f",
"pc8f": "pc8f",
"instrf": "instrf",
"stall": "stall",
"flush": "flush",
"clk": "clk",
"pc4d": "pc4d",
"pc8d": "pc8d",
"instrd": "instrd",
"value": 0,
"enable": "enable",
"edge_type": "falling_edge",
"flush_type": "active_high",
"enable_type": "active_high"
}
reg = Ifid.from_dict(config, hooks)
def test_run(self):
"Prove correct combinational output given signals"
c0 = Constant(8, 150)
c1 = Constant(8, 5)
c2 = Constant(8, 255)
s = Bus(2, 0)
y = Bus(8, 1)
m = Mux(8, [c0, c1, c2], s, y)
m.run()
self.assertTrue(y.read() == c0.read())
s.write(1)
m.run()
self.assertTrue(y.read() == c1.read())
s.write(2)
m.run()
self.assertTrue(y.read() == c2.read())
s.write(3)
m.run()
self.assertTrue(y.read() == 0)
s.write(0)
m = Mux(8, [c0, c1, c2], s)
m.run()
def test_run(self):
"""
tests the memory's run function
"""
ad = Bus(32, 0)
rst = Bus(1, 0)
rd = Bus(32, 0)
mem = ProgramMemory(ad, rst, rd, default_size=32)
# "flash" data to program memory
data = []
for i in range(0, 32):
data.append(i + 1)
msg = mem.modify({'start': 0, 'data': data})
# read from memory validating "programming"
for i in range(0, 8):
ad.write(i * 4)
mem.run()
word = 0
for j in range(0, 4):
word |= data[i * 4 + j] << (32 - ((j + 1) * 8))
self.assertEqual(rd.read(), word)
# test clear message proving empty
mem.clear()
msg = mem.inspect()
self.assertEqual(len(msg['state'].keys()), 0)
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({"i": Bus(32), "c": Bus(2), "o": Bus(32)})
config = {"input": "i", "ctrl": "c", "output": "o"}
ext = MemoryReadSignExtender.from_dict(config, hooks)
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({"imm": Bus(24), "exts": Bus(2), "imm32": Bus(32)})
config = {"imm": "imm", "exts": "exts", "imm32": "imm32"}
ext = Extender.from_dict(config, hooks)
def test_run(self):
"Test run method"
pc4f = Bus(32)
pc8f = Bus(32)
instrf = Bus(32)
stall = Bus(1)
flush = Bus(1)
clk = Bus(1)
pc4d = Bus(32)
pc8d = Bus(32)
instrd = Bus(32)
ifid = Ifid(pc4f, pc8f, instrf, stall, flush, clk, pc4d, pc8d, instrd)
instrf.write(0xE24AA020) # sub r10, r10, #32
ifid.run()
self.assertNotEqual(instrf.read(), instrd.read())
clk.write(1)
ifid.run()
self.assertEqual(instrf.read(), instrd.read())
clk.write(0)
ifid.run()
clk.write(1)
flush.write(1)
ifid.run()
self.assertNotEqual(instrf.read(), instrd.read())
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({
"clock": Bus(1),
"reset": Bus(1),
"write_enable": Bus(1),
"write_data": Bus(32),
"a1": Bus(4),
"a2": Bus(4),
"a3": Bus(4),
"rd1": Bus(32),
"rd2": Bus(32),
})
config = {
"clock": "clock",
"reset": "reset",
"write_enable": "write_enable",
"write_data": "write_data",
"a1": "a1",
"a2": "a2",
"a3": "a3",
"rd1": "rd1",
"rd2": "rd2",
"edge_type": "falling_edge",
"reset_type": "active_high",
"enable_type": "active_low"
}
reg = RegisterFile.from_dict(config, hooks)
def test_clear(self):
"Tests regfile's clear method"
clk = Bus(1, 0)
rst = Bus(1, 0)
wa = Bus(4, 0)
wd = Bus(8, 10)
ra0 = Bus(4, 0)
ra1 = Bus(4, 0)
rd0 = Bus(8)
rd1 = Bus(8)
en = Bus(1, 0)
rgf = RegisterFile(16, 8, clk, rst, wa, wd, [ra0, ra1], [rd0, rd1], en)
# write data
msg = rgf.modify({'start': 0, 'data': [2, 4]})
msg = rgf.inspect()
self.assertEqual(msg['state'][0], 2)
self.assertEqual(msg['state'][1], 4)
# clear
msg = rgf.clear()
self.assertTrue('success' in msg)
# verify empty
msg = rgf.inspect()
self.assertEqual(msg['state'][0], 0)
self.assertEqual(msg['state'][1], 0)
def test_generate_flushf(self):
"Tests the _generate_flushf method"
pcsrcd = Bus(2)
ra3e = Bus(4)
self.assertEqual(HazardController._generate_flushf(pcsrcd, ra3e), 1)
pcsrcd.write(1)
self.assertEqual(HazardController._generate_flushf(pcsrcd, ra3e), 0)
pcsrcd.write(2)
ra3e.write(0xF)
self.assertEqual(HazardController._generate_flushf(pcsrcd, ra3e), 1)
def test_inspect(self):
"Verifies hook inspect for valid return"
clk = Bus(1, 0)
rst = Bus(1, 0)
d_bus = Bus(8, 0)
q_bus = Bus(8, 0)
reg = Register(8, clk, rst, d_bus, q_bus, 1)
ins = reg.inspect()
self.assertTrue(ins['type'] == 'register')
self.assertTrue(ins['size'] == 8)
self.assertTrue(ins['state'] == 1)
def test_out_of_bounds(self):
"Test for valid control signal that extends past defined"
c0 = Constant(8, 150)
c1 = Constant(8, 5)
c2 = Constant(8, 255)
s = Bus(2, 0)
y = Bus(8, 1)
m = Mux(8, [c0, c1, c2], s, y)
s.write(3)
m.run()
self.assertTrue(y.read() == 0) # prove valid overflow
def test_generate_fwds(self):
"Tests the _generate_fwds method"
ra3m = Bus(4)
ra3w = Bus(4)
memwrm = Bus(1)
self.assertEqual(HazardController._generate_fwds(ra3m, ra3w, memwrm),
0)
ra3m.write(8)
ra3w.write(8)
memwrm.write(1)
self.assertEqual(HazardController._generate_fwds(ra3m, ra3w, memwrm),
1)
def __init__(self, c_in, v_in, n_in, z_in, rst, clk, en, c_out, v_out, n_out,
z_out, default_state=DEFAULT_STATE, edge_type=DEFAULT_LATCH_TYPE,
reset_type=DEFAULT_RESET_TYPE, enable_type=DEFAULT_ENABLE_TYPE):
"""
Constructor will check for valid parameters, exception thrown on invalid
Parameters
c_in: 1-bit input of 'c'
v_in: 1-bit input of 'v'
n_in: 1-bit input of 'n'
z_in: 1-bit input of 'z'
rst: Register reset
clk: Register clock
en: Register write enable
c_out: 1-bit output of 'c'
v_out: 1-bit output of 'v'
n_out: 1-bit output of 'n'
z_out: 1-bit output of 'z'
default_state: Initial 4-bit state of ALU Flag
edge_type: Clock state change to store flags
reset_type: Asynchronous reset to default_state value
enable_type: State to allow write to register
"""
if not isinstance(c_in, iBusRead) or not c_in.size() == 1:
raise TypeError('c in must be a 1-bit readable bus')
if not isinstance(v_in, iBusRead) or not v_in.size() == 1:
raise TypeError('v in must be a 1-bit readable bus')
if not isinstance(n_in, iBusRead) or not n_in.size() == 1:
raise TypeError('n in must be a 1-bit readable bus')
if not isinstance(z_in, iBusRead) or not z_in.size() == 1:
raise TypeError('z in must be a 1-bit readable bus')
if not isinstance(c_out, iBusWrite) or not c_out.size() == 1:
raise TypeError('c out must be a 1-bit readable bus')
if not isinstance(v_out, iBusWrite) or not v_out.size() == 1:
raise TypeError('v out must be a 1-bit readable bus')
if not isinstance(n_out, iBusWrite) or not n_out.size() == 1:
raise TypeError('n out must be a 1-bit readable bus')
if not isinstance(z_out, iBusWrite) or not z_out.size() == 1:
raise TypeError('z out must be a 1-bit readable bus')
self._flag_in = Bus(4)
self._join = BusJoin([c_in, v_in, n_in, z_in], self._flag_in)
self._flag_out = Bus(4)
self._subset = BusSubset(self._flag_out, [c_out, v_out, n_out, z_out],
[(0, 1), (1, 2), (2, 3), (3, 4)])
Register.__init__(self, 4, clk, rst, self._flag_in, self._flag_out,
default_state, edge_type, reset_type, en, enable_type)
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({
"a": Bus(32),
"b": Bus(32),
"alus": Bus(4),
"f": Bus(32),
"c": Bus(1),
"v": Bus(1),
"n": Bus(1),
"z": Bus(1)
})
config = {
"input_a": "a",
"input_b": "b",
"alus": "alus",
"output_f": "f",
"output_c": "c",
"output_v": "v",
"output_n": "n",
"output_z": "z"
}
alu = Alu.from_dict(config, hooks)
def test_construct_package_param(self):
"""Prove construction works with specified package"""
package_manager.set_default_packages(["core"]) # Default of module
components = OrderedDict({
"imm": Bus(24),
"exts": Bus(2),
"imm32": Bus(32)
})
obj_extender = package_manager.construct("Extender", {
"imm": "imm",
"exts": "exts",
"imm32": "imm32"
}, ["arm"], components)
components.update({"extender": obj_extender})
def test_constructor(self):
"Constructor with valid and invalid configuration"
clk = Bus(1, 0)
rst = Bus(1, 0)
wa = Bus(4, 0)
wd = Bus(32, 10)
ra0 = Bus(4, 0)
ra1 = Bus(4, 0)
rd0 = Bus(32)
rd1 = Bus(32)
en = Bus(1, 0)
# just prove that the constructor accepts data when filled, rest is
# tested under the core component
reg = RegisterFile(clk, rst, en, wd, ra0, ra1, wa, rd0, rd1)
reg = RegisterFile(clk,
rst,
en,
wd,
ra0,
ra1,
wa,
rd0,
rd1,
edge_type=Latch_Type.BOTH_EDGE)
reg = RegisterFile(clk,
rst,
en,
wd,
ra0,
ra1,
wa,
rd0,
rd1,
reset_type=Logic_States.ACTIVE_HIGH)
reg = RegisterFile(clk,
rst,
en,
wd,
ra0,
ra1,
wa,
rd0,
rd1,
enable_type=Logic_States.ACTIVE_LOW)
reg = RegisterFile(clk, rst, en, wd, ra0, ra1, wa, rd0, rd1,
Latch_Type.RISING_EDGE, Logic_States.ACTIVE_HIGH,
Logic_States.ACTIVE_LOW)
def test_inspect(self):
"Check inspect for valid data presentation"
b = Bus(8, 255)
ins = b.inspect()
self.assertTrue(ins['type'] == 'logic')
self.assertTrue(ins['size'] == 8)
self.assertTrue(ins['state'] == 255)
def test_run(self):
"Prove correct combinational output given signals"
cin = Constant(1, 1)
c1 = Constant(8, 1)
c2 = Constant(8, 254)
y0 = Bus(8)
cout = Bus(1)
a = Adder(8, c1, c2, y0, cin, cout)
a.run()
self.assertTrue(y0.read() == 0)
self.assertTrue(cout.read() == 1)
a.run(50)
self.assertTrue(y0.read() == 0)
self.assertTrue(cout.read() == 1)
def test_run(self):
"Verifies correct time based simulation"
clk = Bus(1, 0)
rst = Bus(1, 0)
d_bus = Bus(8, 10)
q_bus = Bus(8, 0)
en = Bus(1, 0)
reg = Register(8, clk, rst, d_bus, q_bus, 0, Latch_Type.RISING_EDGE,
Logic_States.ACTIVE_HIGH, en, Logic_States.ACTIVE_HIGH)
en.write(0)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 0)
en.write(1)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 0)
en.write(0)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 0)
en.write(1)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 0)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 0)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 10)
d_bus.write(15)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 10)
rst.write(1)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 0)
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({
"a": Bus(2),
"b": Bus(2),
"slct": Bus(1),
"o": Bus(2)
})
config = {
"width": 2,
"inputs": ["a", "b"],
"select": "slct",
"output": "o"
}
mux = Mux.from_dict(config, hooks)
def test_large_mux(self):
"Test mux for large size to validate scaling algorithm"
c0 = Constant(8, 150)
c1 = Constant(8, 5)
c2 = Constant(8, 255)
c3 = Constant(8, 150)
c4 = Constant(8, 5)
c5 = Constant(8, 255)
c6 = Constant(8, 150)
c7 = Constant(8, 5)
s = Bus(3, 0)
y = Bus(8, 1)
m = Mux(8, [c0, c1, c2, c3, c4, c5, c6], s, y)
c8 = Constant(8, 255)
s = Bus(4, 0)
m = Mux(8, [c0, c1, c2, c3, c4, c5, c6, c7, c8], s, y)
def test_run(self):
"Prove correct combinational output given signals"
c0 = Constant(16, 0xAAAA)
b0 = Bus(4)
b1 = Bus(8)
b2 = Bus(2)
b3 = Bus(2)
b4 = Bus(1)
bs = BusSubset(c0, [b0, b1, b2, b3, b4], [(0, 4), (4, 12), (12, 14),
(14, 16), (3, 4)])
bs.run()
self.assertTrue(b0.read() == 0x0A)
self.assertTrue(b1.read() == 0xAA)
self.assertTrue(b2.read() == 0x02)
self.assertTrue(b3.read() == 0x02)
self.assertTrue(b4.read() == 1)
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({
"address" : Bus(32),
"write" : Bus(32),
"we" : Bus(1),
"reset" : Bus(1),
"clock" : Bus(1),
"read" : Bus(32),
"mode" : Bus(2)
})
config = {
"address" : "address",
"write" : "write",
"write_enable" : "we",
"reset" : "reset",
"clock" : "clock",
"read" : "read",
"mode" : "mode",
"size" : 32,
"value" : 255,
"edge_type" : "rising_edge",
"reset_type" : "active_high",
"enable_type" : "active_high"
}
mem = DataMemory.from_dict(config,hooks)
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({
"clk": Bus(1),
"rst": Bus(1),
"wa": Bus(4),
"wd": Bus(32),
"ra": Bus(4),
"rd": Bus(32),
"en": Bus(1)
})
config = {
"size": 16,
"width": 32,
"clock": "clk",
"reset": "rst",
"write_address": "wa",
"write_data": "wd",
"read_addresses": ["ra"],
"read_datas": ["rd"],
"enable": "en",
"value": 255,
"edge_type": "rising_edge",
"reset_type": "active_high",
"enable_type": "active_high"
}
regFile = RegisterFile.from_dict(config, hooks)
def test_from_dict(self):
"Validates dictionary constructor"
hooks = OrderedDict({
"i1": Constant(8, 0x0F),
"o1": Bus(4),
"o2": Bus(4)
})
config = {
"input": "i1",
"outputs": ["o1", "o2"],
"bounds": [[0, 4], [4, 8]]
}
subset = BusSubset.from_dict(config, hooks)
subset.run()
self.assertEqual(hooks["o1"].read(), 0xF)
self.assertEqual(hooks["o2"].read(), 0x0)