def test_out_of_bounds(self): "Test for valid control signal that extends past defined" c0 = Constant(8, 150) c1 = Constant(8, 5) c2 = Constant(8, 255) s = Bus(2, 0) y = Bus(8, 1) m = Mux(8, [c0, c1, c2], s, y) s.write(3) m.run() self.assertTrue(y.read() == 0) # prove valid overflow
def test_large_mux(self): "Test mux for large size to validate scaling algorithm" c0 = Constant(8, 150) c1 = Constant(8, 5) c2 = Constant(8, 255) c3 = Constant(8, 150) c4 = Constant(8, 5) c5 = Constant(8, 255) c6 = Constant(8, 150) c7 = Constant(8, 5) s = Bus(3, 0) y = Bus(8, 1) m = Mux(8, [c0, c1, c2, c3, c4, c5, c6], s, y) c8 = Constant(8, 255) s = Bus(4, 0) m = Mux(8, [c0, c1, c2, c3, c4, c5, c6, c7, c8], s, y)
def test_from_dict(self): "Validates dictionary constructor" hooks = OrderedDict({ "a": Bus(2), "b": Bus(2), "slct": Bus(1), "o": Bus(2) }) config = { "width": 2, "inputs": ["a", "b"], "select": "slct", "output": "o" } mux = Mux.from_dict(config, hooks)
def test_run(self): "Prove correct combinational output given signals" c0 = Constant(8, 150) c1 = Constant(8, 5) c2 = Constant(8, 255) s = Bus(2, 0) y = Bus(8, 1) m = Mux(8, [c0, c1, c2], s, y) m.run() self.assertTrue(y.read() == c0.read()) s.write(1) m.run() self.assertTrue(y.read() == c1.read()) s.write(2) m.run() self.assertTrue(y.read() == c2.read()) s.write(3) m.run() self.assertTrue(y.read() == 0) s.write(0) m = Mux(8, [c0, c1, c2], s) m.run()
def test_constructor(self): "Constructor with valid and invalid configuration" c0 = Constant(8, 150) c1 = Constant(8, 5) c2 = Constant(8, 255) s = Bus(2, 0) y = Bus(8, 1) with self.assertRaises(TypeError): m = Mux('0', [c0, c1, c2], s, y) with self.assertRaises(TypeError): m = Mux(0, [c0, c1, c2], s, y) with self.assertRaises(TypeError): m = Mux(8, None, s, y) with self.assertRaises(TypeError): m = Mux(8, [], s, y) with self.assertRaises(TypeError): m = Mux(8, [None], s, y) with self.assertRaises(TypeError): m = Mux(8, ['0', '1', '2'], s, y) with self.assertRaises(TypeError): c = Constant(1, 0) m = Mux(8, [c1, c0, c], s, y) with self.assertRaises(TypeError): m = Mux(8, [c1, c0], None, y) with self.assertRaises(ValueError): s0 = Bus(8, 0) m = Mux(8, [c1, c0], s0, y) with self.assertRaises(ValueError): m = Mux(8, [c1, c0], s, y) with self.assertRaises(TypeError): m = Mux(8, [c1, c0, c2], s, '0') with self.assertRaises(ValueError): y0 = Bus(2) m = Mux(8, [c1, c0, c2], s, y0) m = Mux(8, [c0, c1, c2], s, y) m = Mux(8, [c0, c1, c2], s)
def generate_single_cycle_architecture(): "Illustrates the necessary process to construct an architecture" # define system resources clk = Clock(10, 0) rst = Reset(0) hooks = OrderedDict([('clk', clk), ('rst', rst)]) # define input hooks and constants hooks.update({'const8': Constant(32, 8)}) hooks.update({'const4': Constant(32, 4)}) hooks.update({'const14': Constant(4, 14)}) # define buses hooks.update({'pc': Bus(32, 0)}) hooks.update({'pc8': Bus(32, 0)}) hooks.update({'pc4': Bus(32, 0)}) hooks.update({'instr': Bus(32, 0)}) hooks.update({'instr_23_0': Bus(24, 0)}) hooks.update({'instr_19_16': Bus(4, 0)}) hooks.update({'instr_3_0': Bus(4, 0)}) hooks.update({'instr_15_12': Bus(4, 0)}) hooks.update({'instr_11_8': Bus(4, 0)}) hooks.update({'instr_31_28': Bus(4, 0)}) hooks.update({'instr_27_26': Bus(2, 0)}) hooks.update({'instr_25_20': Bus(6, 0)}) hooks.update({'instr_4_4': Bus(1, 0)}) hooks.update({'imm32': Bus(32, 0)}) hooks.update({'ra1': Bus(4, 0)}) hooks.update({'ra2': Bus(4, 0)}) hooks.update({'ra3': Bus(4, 0)}) hooks.update({'rwd': Bus(32, 0)}) hooks.update({'rd1': Bus(32, 0)}) hooks.update({'rd2': Bus(32, 0)}) hooks.update({'alub': Bus(32, 0)}) hooks.update({'branch': Bus(32, 0)}) hooks.update({'aluf': Bus(32, 0)}) hooks.update({'aluc': Bus(1, 0)}) hooks.update({'aluv': Bus(1, 0)}) hooks.update({'alun': Bus(1, 0)}) hooks.update({'aluz': Bus(1, 0)}) hooks.update({'aluflag': Bus(4, 0)}) hooks.update({'flag': Bus(4, 0)}) hooks.update({'c': Bus(1, 0)}) hooks.update({'v': Bus(1, 0)}) hooks.update({'n': Bus(1, 0)}) hooks.update({'z': Bus(1, 0)}) hooks.update({'memrd': Bus(32, 0)}) hooks.update({'wdb': Bus(32, 0)}) hooks.update({'pcwb': Bus(32, 0)}) # control signals hooks.update({'pcwr': Bus(1, 0)}) hooks.update({'regsa': Bus(1, 0)}) hooks.update({'regdst': Bus(2, 0)}) hooks.update({'regwrs': Bus(2, 0)}) hooks.update({'wdbs': Bus(1, 0)}) hooks.update({'regwr': Bus(1, 0)}) hooks.update({'exts': Bus(2, 0)}) hooks.update({'alu8rcb': Bus(1, 0)}) hooks.update({'alus': Bus(4, 0)}) hooks.update({'aluflagwr': Bus(1, 0)}) hooks.update({'memwr': Bus(1, 0)}) hooks.update({'regsrc': Bus(1, 0)}) hooks.update({'pcsrc': Bus(2, 0)}) # generate components # FETCH entities = OrderedDict([('clk', clk)]) entities.update({'pc_reg': Register(32, hooks['clk'], hooks['rst'], hooks['pcwb'], hooks['pc'], 0, enable=hooks['pcwr'], edge_type=Latch_Type.FALLING_EDGE)}) entities.update({'add8': Adder(32, hooks['pc'], hooks['const8'], hooks['pc8'])}) entities.update({'add4': Adder(32, hooks['pc'], hooks['const4'], hooks['pc4'])}) entities.update({'progmem': ProgramMemory(hooks['pc'], hooks['rst'], hooks['instr'])}) # DECODE entities.update({'instr_subset': BusSubset(hooks['instr'], [hooks['instr_23_0'], hooks['instr_19_16'], hooks['instr_3_0'], hooks['instr_15_12'], hooks['instr_11_8'], hooks['instr_31_28'], hooks['instr_27_26'], hooks['instr_25_20'], hooks['instr_4_4']], [(0, 24), (16, 20), (0, 4), (12, 16), (8, 12), (28, 32), (26, 28), (20, 26), (4, 5)])}) entities.update({'controller': ControllerSingleCycle(hooks['instr_31_28'], hooks['instr_27_26'], hooks['instr_25_20'], hooks['instr_15_12'], hooks['instr_4_4'], hooks['c'], hooks['v'], hooks['n'], hooks['z'], hooks['pcsrc'], hooks['pcwr'], hooks['regsa'], hooks['regdst'], hooks['regwrs'], hooks['regwr'], hooks['exts'], hooks['alu8rcb'], hooks['alus'], hooks['aluflagwr'], hooks['memwr'], hooks['regsrc'], hooks['wdbs'])}) entities.update({'ra1_mux': Mux(4, [hooks['instr_3_0'], hooks['instr_19_16']], hooks['regsa'], hooks['ra1'])}) entities.update({'ra2_mux': Mux(4, [hooks['instr_11_8'], hooks['instr_3_0'], hooks['instr_15_12']], hooks['regdst'], hooks['ra2'])}) entities.update({'ra3_mux': Mux(4, [hooks['instr_19_16'], hooks['instr_15_12'], hooks['const14']], hooks['regwrs'], hooks['ra3'])}) entities.update({'rwd_mux': Mux(32, [hooks['wdb'], hooks['pc4']], hooks['wdbs'], hooks['rwd'])}) entities.update({'extimm': Extender(hooks['instr_23_0'], hooks['exts'], hooks['imm32'])}) entities.update({'regfile': RegisterFile(hooks['clk'], hooks['rst'], hooks['regwr'], hooks['rwd'], hooks['ra1'], hooks['ra2'], hooks['ra3'], hooks['rd1'], hooks['rd2'])}) # EXECUTE entities.update({'alu_mux': Mux(32, [hooks['imm32'], hooks['rd2']], hooks['alu8rcb'], hooks['alub'])}) entities.update({'add_br': Adder(32, hooks['pc8'], hooks['imm32'], hooks['branch'])}) entities.update({'alu': Alu(hooks['rd1'], hooks['alub'], hooks['alus'], hooks['aluf'], hooks['aluc'], hooks['aluv'], hooks['alun'], hooks['aluz'])}) entities.update({'aluflag_reg': ALUFlagRegister(hooks['aluc'], hooks['aluv'], hooks['alun'], hooks['aluz'], hooks['rst'], hooks['clk'], hooks['aluflagwr'], hooks['c'], hooks['v'], hooks['n'], hooks['z'])}) # MEMORY & WRITE-BACK entities.update({'datamem': DataMemory(hooks['aluf'], hooks['rd2'], hooks['memwr'], hooks['rst'], hooks['clk'], hooks['memrd'])}) entities.update({'wdb_mux': Mux(32, [hooks['memrd'], hooks['aluf']], hooks['regsrc'], hooks['wdb'])}) entities.update({'pcwb_mux': Mux(32, [hooks['branch'], hooks['pc4'], hooks['wdb']], hooks['pcsrc'], hooks['pcwb'])}) # place memory (Internal) hooks into hook list hooks.update({'pc_reg': entities['pc_reg']}) hooks.update({'progmem': entities['progmem']}) hooks.update({'regfile': entities['regfile']}) hooks.update({'aluflag_reg': entities['aluflag_reg']}) hooks.update({'datamem': entities['datamem']}) hooks.update({'controller': entities['controller']}) # generate simulatable architecture arch = Architecture(0.0001, clk, rst, None, hooks, entities) return arch, hooks
def generate_pipeline_architecture(): "Illustrates the necessary process to construct an architecture" ########## define system resources ########## clk = Clock(10, 0) rst = Reset(0) hooks = OrderedDict([('clk', clk), ('rst', rst)]) ########## define input hooks and constants ########## hooks.update({'const4': Constant(32, 4)}) hooks.update({'const8': Constant(32, 8)}) hooks.update({'const14': Constant(4, 14)}) ########## define buses ########## hooks.update({'pc': Bus(32, 0)}) hooks.update({'pc4f': Bus(32, 0)}) hooks.update({'pc4d': Bus(32, 0)}) hooks.update({'pc4e': Bus(32, 0)}) hooks.update({'pc4m': Bus(32, 0)}) hooks.update({'pc4w': Bus(32, 0)}) hooks.update({'pc8f': Bus(32, 0)}) hooks.update({'pc8d': Bus(32, 0)}) hooks.update({'braddr': Bus(32, 0)}) hooks.update({'nextaddr': Bus(32, 0)}) hooks.update({'instrf': Bus(32, 0)}) hooks.update({'instrd': Bus(32, 0)}) hooks.update({'instrd_31_28': Bus(4, 0)}) hooks.update({'instrd_27_26': Bus(2, 0)}) hooks.update({'instrd_25_20': Bus(6, 0)}) hooks.update({'instrd_19_16': Bus(4, 0)}) hooks.update({'instrd_15_12': Bus(4, 0)}) hooks.update({'instrd_11_8': Bus(4, 0)}) hooks.update({'instrd_4': Bus(1, 0)}) hooks.update({'instrd_3_0': Bus(4, 0)}) hooks.update({'instrd_23_0': Bus(24, 0)}) hooks.update({'imm32d': Bus(32, 0)}) hooks.update({'imm32e': Bus(32, 0)}) hooks.update({'rdm': Bus(32, 0)}) hooks.update({'rdw': Bus(32, 0)}) hooks.update({'rd1': Bus(32, 0)}) hooks.update({'rd2': Bus(32, 0)}) hooks.update({'rd1d': Bus(32, 0)}) hooks.update({'rd2d': Bus(32, 0)}) hooks.update({'rd1e': Bus(32, 0)}) hooks.update({'rd2e': Bus(32, 0)}) hooks.update({'rd2m': Bus(32, 0)}) hooks.update({'ra1d': Bus(4, 0)}) hooks.update({'ra2d': Bus(4, 0)}) hooks.update({'ra3d': Bus(4, 0)}) hooks.update({'ra1e': Bus(4, 0)}) hooks.update({'ra2e': Bus(4, 0)}) hooks.update({'ra3e': Bus(4, 0)}) hooks.update({'ra3m': Bus(4, 0)}) hooks.update({'ra3w': Bus(4, 0)}) hooks.update({'fe': Bus(32, 0)}) hooks.update({'fm': Bus(32, 0)}) hooks.update({'fw': Bus(32, 0)}) hooks.update({'alub': Bus(32, 0)}) hooks.update({'aluc': Bus(1, 0)}) hooks.update({'aluv': Bus(1, 0)}) hooks.update({'alun': Bus(1, 0)}) hooks.update({'aluz': Bus(1, 0)}) hooks.update({'c': Bus(1, 0)}) hooks.update({'v': Bus(1, 0)}) hooks.update({'n': Bus(1, 0)}) hooks.update({'z': Bus(1, 0)}) hooks.update({'aluflag': Bus(4, 0)}) hooks.update({'flag': Bus(4, 0)}) hooks.update({'data': Bus(32, 0)}) hooks.update({'wd': Bus(32, 0)}) hooks.update({'wd3': Bus(32, 0)}) ########## control signals ########## # decode stage hooks.update({'pcsrcd': Bus(2, 0)}) hooks.update({'pcwrd': Bus(1, 0)}) hooks.update({'regsad': Bus(1, 0)}) hooks.update({'regdstd': Bus(2, 0)}) hooks.update({'regwrsd': Bus(2, 0)}) hooks.update({'regwrd': Bus(1, 0)}) hooks.update({'extsd': Bus(2, 0)}) hooks.update({'alusrcbd': Bus(1, 0)}) hooks.update({'alusd': Bus(4, 0)}) hooks.update({'aluflagwrd': Bus(1, 0)}) hooks.update({'memwrd': Bus(1, 0)}) hooks.update({'regsrcd': Bus(1, 0)}) hooks.update({'wd3sd': Bus(1, 0)}) # execute stage hooks.update({'regwre': Bus(1, 0)}) hooks.update({'alusrcbe': Bus(1, 0)}) hooks.update({'aluse': Bus(4, 0)}) hooks.update({'aluflagwre': Bus(1, 0)}) hooks.update({'memwre': Bus(1, 0)}) hooks.update({'regsrce': Bus(1, 0)}) hooks.update({'wd3se': Bus(1, 0)}) # memory stage hooks.update({'regwrm': Bus(1, 0)}) hooks.update({'memwrm': Bus(1, 0)}) hooks.update({'regsrcm': Bus(1, 0)}) hooks.update({'wd3sm': Bus(1, 0)}) # write back stage hooks.update({'regwrw': Bus(1, 0)}) hooks.update({'regsrcw': Bus(1, 0)}) hooks.update({'wd3sw': Bus(1, 0)}) ########## hazard control signals ########## hooks.update({'fwda': Bus(3, 0)}) hooks.update({'fwdb': Bus(3, 0)}) hooks.update({'fwds': Bus(1, 0)}) hooks.update({'stallf': Bus(1, 0)}) hooks.update({'flushf': Bus(1, 0)}) hooks.update({'flushd': Bus(1, 0)}) ########## generate components ########## entities = OrderedDict([('clk', clk)]) # memwb entities.update({ 'memwb': Memwb(hooks['pc4m'], hooks['regwrm'], hooks['regsrcm'], hooks['wd3sm'], hooks['fm'], hooks['rdm'], hooks['ra3m'], hooks['clk'], hooks['pc4w'], hooks['regwrw'], hooks['regsrcw'], hooks['wd3sw'], hooks['fw'], hooks['rdw'], hooks['ra3w']) }) # exmem entities.update({ 'exmem': Exmem(hooks['pc4e'], hooks['regwre'], hooks['memwre'], hooks['regsrce'], hooks['wd3se'], hooks['rd2'], hooks['fe'], hooks['ra3e'], hooks['clk'], hooks['pc4m'], hooks['regwrm'], hooks['memwrm'], hooks['regsrcm'], hooks['wd3sm'], hooks['fm'], hooks['rd2m'], hooks['ra3m']) }) # idex entities.update({ 'idex': Idex(hooks['pc4d'], hooks['regwrd'], hooks['alusrcbd'], hooks['alusd'], hooks['aluflagwrd'], hooks['memwrd'], hooks['regsrcd'], hooks['wd3sd'], hooks['rd1d'], hooks['rd2d'], hooks['imm32d'], hooks['ra1d'], hooks['ra2d'], hooks['ra3d'], hooks['flushd'], hooks['clk'], hooks['pc4e'], hooks['regwre'], hooks['alusrcbe'], hooks['aluse'], hooks['aluflagwre'], hooks['memwre'], hooks['regsrce'], hooks['wd3se'], hooks['rd1e'], hooks['rd2e'], hooks['imm32e'], hooks['ra1e'], hooks['ra2e'], hooks['ra3e']) }) # ifid entities.update({ 'ifid': Ifid(hooks['pc4f'], hooks['pc8f'], hooks['instrf'], hooks['stallf'], hooks['flushf'], hooks['clk'], hooks['pc4d'], hooks['pc8d'], hooks['instrd']) }) # fetch entities.update({ 'addr_mux': Mux(32, [hooks['braddr'], hooks['pc4d'], hooks['fe']], hooks['pcsrcd'], hooks['nextaddr']) }) entities.update({ 'pc_reg': Register(32, hooks['clk'], hooks['rst'], hooks['nextaddr'], hooks['pc'], 0, enable=hooks['pcwrd']) }) entities.update( {'add8': Adder(32, hooks['pc'], hooks['const8'], hooks['pc8f'])}) entities.update( {'add4': Adder(32, hooks['pc'], hooks['const4'], hooks['pc4f'])}) entities.update( {'progmem': ProgramMemory(hooks['pc'], hooks['rst'], hooks['instrf'])}) # decode entities.update({ 'instr_subset': BusSubset(hooks['instrd'], [ hooks['instrd_23_0'], hooks['instrd_31_28'], hooks['instrd_27_26'], hooks['instrd_25_20'], hooks['instrd_19_16'], hooks['instrd_15_12'], hooks['instrd_11_8'], hooks['instrd_4'], hooks['instrd_3_0'] ], [(0, 24), (28, 32), (26, 28), (20, 26), (16, 20), (12, 16), (8, 12), (4, 5), (0, 4)]) }) entities.update({ 'controller': ControllerPipeline(hooks['instrd_31_28'], hooks['instrd_27_26'], hooks['instrd_25_20'], hooks['instrd_15_12'], hooks['instrd_4'], hooks['c'], hooks['v'], hooks['n'], hooks['z'], hooks['stallf'], hooks['pcsrcd'], hooks['pcwrd'], hooks['regsad'], hooks['regdstd'], hooks['regwrsd'], hooks['regwrd'], hooks['extsd'], hooks['alusrcbd'], hooks['alusd'], hooks['aluflagwrd'], hooks['memwrd'], hooks['regsrcd'], hooks['wd3sd']) }) entities.update({ 'ra1_mux': Mux(4, [hooks['instrd_3_0'], hooks['instrd_19_16']], hooks['regsad'], hooks['ra1d']) }) entities.update({ 'ra2_mux': Mux(4, [hooks['instrd_11_8'], hooks['instrd_3_0'], hooks['instrd_15_12']], hooks['regdstd'], hooks['ra2d']) }) entities.update({ 'ra3_mux': Mux(4, [hooks['instrd_19_16'], hooks['instrd_15_12'], hooks['const14']], hooks['regwrsd'], hooks['ra3d']) }) entities.update({ 'extimm': Extender(hooks['instrd_23_0'], hooks['extsd'], hooks['imm32d']) }) entities.update({ 'add_branch': Adder(32, hooks['pc8d'], hooks['imm32d'], hooks['braddr']) }) entities.update({ 'regfile': RegisterFile(hooks['clk'], hooks['rst'], hooks['regwrw'], hooks['wd'], hooks['ra1d'], hooks['ra2d'], hooks['ra3w'], hooks['rd1d'], hooks['rd2d'], edge_type=Latch_Type.FALLING_EDGE) }) # execute entities.update({ 'hazard_controller': HazardController(hooks['ra1e'], hooks['ra2e'], hooks['ra3e'], hooks['ra3m'], hooks['ra3w'], hooks['regwrm'], hooks['regwrw'], hooks['regsrcm'], hooks['regsrcw'], hooks['memwrm'], hooks['pcsrcd'], hooks['fwda'], hooks['fwdb'], hooks['fwds'], hooks['stallf'], hooks['flushf'], hooks['flushd']) }) entities.update({ 'fwda_mux': Mux(32, [ hooks['rd1e'], hooks['fw'], hooks['fm'], hooks['rdm'], hooks['rdw'] ], hooks['fwda'], hooks['rd1']) }) entities.update({ 'fwdb_mux': Mux(32, [ hooks['rd2e'], hooks['fw'], hooks['fm'], hooks['rdm'], hooks['rdw'] ], hooks['fwdb'], hooks['rd2']) }) entities.update({ 'alu_mux': Mux(32, [hooks['imm32e'], hooks['rd2']], hooks['alusrcbe'], hooks['alub']) }) entities.update({ 'alu': Alu(hooks['rd1'], hooks['alub'], hooks['aluse'], hooks['fe'], hooks['aluc'], hooks['aluv'], hooks['alun'], hooks['aluz']) }) entities.update({ 'aluflag_join': BusJoin([hooks['aluc'], hooks['aluv'], hooks['alun'], hooks['aluz']], hooks['aluflag']) }) entities.update({ 'aluflag_reg': Register(4, hooks['clk'], hooks['rst'], hooks['aluflag'], hooks['flag'], enable=hooks['aluflagwre']) }) entities.update({ 'flag_subset': BusSubset(hooks['flag'], [hooks['c'], hooks['v'], hooks['n'], hooks['z']], [(0, 1), (1, 2), (2, 3), (3, 4)]) }) # writeback entities.update({ 'wd3_mux': Mux(32, [hooks['rdw'], hooks['fw']], hooks['regsrcw'], hooks['wd3']) }) entities.update({ 'rwd_mux': Mux(32, [hooks['wd3'], hooks['pc4w']], hooks['wd3sw'], hooks['wd']) }) # memory entities.update({ 'fwds_mux': Mux(32, [hooks['rd2m'], hooks['wd3']], hooks['fwds'], hooks['data']) }) entities.update({ 'datamem': DataMemory(hooks['fm'], hooks['data'], hooks['memwrm'], hooks['rst'], hooks['clk'], hooks['rdm']) }) # place memory (Internal) hooks into hook list hooks.update({'pc_reg': entities['pc_reg']}) hooks.update({'progmem': entities['progmem']}) hooks.update({'regfile': entities['regfile']}) hooks.update({'aluflag_reg': entities['aluflag_reg']}) hooks.update({'datamem': entities['datamem']}) hooks.update({'controller': entities['controller']}) #hooks.update({'hazard_controller': entities['hazard_controller']}) hooks.update({'ifid': entities['ifid']}) hooks.update({'idex': entities['idex']}) hooks.update({'exmem': entities['exmem']}) hooks.update({'memwb': entities['memwb']}) # generate simulatable architecture arch = Architecture(0.0001, clk, rst, None, hooks, entities) return arch, hooks
v_bus = Bus(1, 0) n_bus = Bus(1, 0) z_bus = Bus(1, 0) ss0_bus = Bus(8, 0) ss1_bus = Bus(8, 0) ss2_bus = Bus(8, 0) ss3_bus = Bus(8, 0) bj0 = Bus(32, 0) reg = Register(32, clk, rst, d_bus, q_bus) add = Adder(32, q_bus, c1, d_bus) regFile = Register_File(clk, rst, c2, d_bus, address, address, address, q_bus, m_bus) m = Mux(32, [q_bus, m_bus], c2, f_bus) alu = Alu(f_bus, q_bus, Bus(1, 0), r_bus, c_bus, v_bus, n_bus, z_bus) subset = BusSubset(q_bus, [ss0_bus, ss1_bus, ss2_bus, ss3_bus], [(0, 8), (8, 16), (16, 24), (24, 32)]) join = BusJoin([ss3_bus, ss2_bus, ss1_bus, ss0_bus], bj0) add.run() reg.run() regFile.run() m.run() alu.run() subset.run() join.run()