def STM32F091xC_fixup(d):
d.soc_name = 'STM32F091xC'
d.cpu_info.deviceNumInterrupts = 32
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# More decode for the DBGMCU registers
f = d.DBGMCU.IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBGMCU.IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F'), _STM32F091xC_altfunc)
# TODO: RCC.AHBENR.IOPEEN is missing from the svd
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 32 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('flash_system', 0x1fffd800, 8 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 256 << 10, None,
'flash main memory'))
d.insert(
soc.make_peripheral('flash_option', 0x1ffff800, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('UID', 0x1ffff7ac, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1ffff7cc, 2, _flash_size_regset,
'Flash Size'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 24 << 10)
def STM32F429xI_fixup(d):
d.soc_name = 'STM32F429xI'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 90
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# more decode for the DBG registers
f = d.DBG.DBGMCU_IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBG.DBGMCU_IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# fix up the OSPEEDR labels ST messed up
for x in ('A','B','C','D','E','F','G','H','I','J','K'):
d.peripherals['GPIO%c' % x].rename_register('GPIOB_OSPEEDR', 'OSPEEDR')
# more decode for the GPIO registers
gpio_decodes(d, ('A','B','C','D','E','F','G','H','I','J','K'), _STM32F429xI_altfunc)
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 256 << 10, None, 'sram'))
d.insert(soc.make_peripheral('ccm_sram', 0x10000000, 64 << 10, None, 'core coupled memory sram'))
d.insert(soc.make_peripheral('flash_system', 0x1fff0000, 30 << 10, None, 'flash system memory'))
d.insert(soc.make_peripheral('flash_main', 0x08000000, 2 << 20, None, 'flash main memory'))
d.insert(soc.make_peripheral('flash_opt_bank1', 0x1fffc000, 16, None, 'flash option memory'))
d.insert(soc.make_peripheral('flash_opt_bank2', 0x1ffec000, 16, None, 'flash option memory'))
d.insert(soc.make_peripheral('flash_otp', 0x1fff7800, 528, None, 'flash otp memory'))
d.insert(soc.make_peripheral('UID', 0x1fff7a10, 12, _uuid_regset, 'Unique Device ID'))
d.insert(soc.make_peripheral('FLASH_SIZE', 0x1fff7a22, 2, _flash_size_regset, 'Flash Size'))
# the size of this peripheral seems wrong
d.OTG_HS_PWRCLK.size = 1 << 10
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def flexspi_decodes(d):
"""setup additional flexspi field decodes not in the svd file"""
p = d.FLEXSPI
for i in range(64):
r = p.registers['LUT%d' % i]
f = r.OPCODE0
f.enumvals = soc.make_enumvals(f, _flexspi_opcode_enumset)
f = r.OPCODE1
f.enumvals = soc.make_enumvals(f, _flexspi_opcode_enumset)
def STM32F407xx_fixup(d):
d.soc_name = 'STM32F407xx'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 82
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# more decode for the DBG registers
f = d.DBG.DBGMCU_IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBG.DBGMCU_IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'),
_STM32F407xx_altfunc)
# additional interrupts
d.insert(
soc.make_interrupt('HASH_RNG_IRQ', 80,
'Hash and RNG global interrupt'))
d.insert(soc.make_interrupt('FPU_IRQ', 81, 'FPU global interrupt'))
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 128 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('ccm_sram', 0x10000000, 8 << 10, None,
'core coupled memory sram'))
d.insert(
soc.make_peripheral('flash_system', 0x1fff0000, 30 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 1 << 20, None,
'flash main memory'))
d.insert(
soc.make_peripheral('flash_option', 0x1fffc000, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('flash_otp', 0x1fff7800, 528, None,
'flash otp memory'))
d.insert(
soc.make_peripheral('UID', 0x1fff7a10, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1fff7a22, 2, _flash_size_regset,
'Flash Size'))
# the size of these peripherals seems wrong
d.OTG_HS_GLOBAL.size = 1 << 10
d.OTG_HS_PWRCLK.size = 1 << 10
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def STM32F427xx_fixup(d):
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 106
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# more decode for the DBG registers
f = d.DBG.DBGMCU_IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBG.DBGMCU_IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'),
_STM32F427xx_altfunc)
# sram
d.insert(soc.make_peripheral('sram', 0x20000000, 256 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('ccm_sram', 0x10000000, 64 << 10, None,
'core coupled memory sram'))
d.insert(
soc.make_peripheral('BKPSRAM', 0x40024000, 4 << 10, None,
'backup sram'))
# flash (rm0090 3.4 table 6))
d.insert(
soc.make_peripheral('flash_otp', 0x1fff7800, 528, None,
'flash otp memory'))
d.insert(
soc.make_peripheral('flash_system', 0x1fff0000, 30 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_opt_bank1', 0x1fffc000, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('flash_opt_bank2', 0x1ffec000, 16, None,
'flash option memory'))
# misc periperhals
d.insert(
soc.make_peripheral('UID', 0x1fff7a10, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1fff7a22, 2, _flash_size_regset,
'Flash Size'))
# the size of this peripheral seems wrong
d.OTG_HS_PWRCLK.size = 1 << 10
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)
def gpio_decodes(d, ports, altfunc):
"""setup additional gpio field decodes not in the svd file"""
for p in ports:
gpio = d.peripherals['GPIO%s' % p]
for i in range(16):
f = gpio.MODER.fields['MODER%d' % i]
f.enumvals = soc.make_enumvals(f, _gpio_moder_enumset)
f = gpio.OTYPER.fields['OT%d' % i]
f.enumvals = soc.make_enumvals(f, _gpio_otyper_enumset)
f = gpio.OSPEEDR.fields['OSPEEDR%d' % i]
f.enumvals = soc.make_enumvals(f, _gpio_ospeedr_enumset)
f = gpio.PUPDR.fields['PUPDR%d' % i]
f.enumvals = soc.make_enumvals(f, _gpio_pupdr_enumset)
if i < 8:
f = gpio.AFRL.fields['AFRL%d' % i]
else:
f = gpio.AFRH.fields['AFRH%d' % i]
f.enumvals = soc.make_enumvals(f, gpio_altfunc_enums(p, i, altfunc))
def STM32F091xC_fixup(d):
d.soc_name = 'STM32F091xC'
d.cpu_info.deviceNumInterrupts = 32
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
# More decode for the DBGMCU registers
f = d.DBGMCU.IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBGMCU.IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A','B','C','D','E','F'), _STM32F091xC_altfunc)
# TODO: RCC.AHBENR.IOPEEN is missing from the svd
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 32 << 10, None, 'sram'))
d.insert(soc.make_peripheral('flash_system', 0x1fffd800, 8 << 10, None, 'flash system memory'))
d.insert(soc.make_peripheral('flash_main', 0x08000000, 256 << 10, None, 'flash main memory'))
d.insert(soc.make_peripheral('flash_option', 0x1ffff800, 16, None, 'flash option memory'))
d.insert(soc.make_peripheral('UID', 0x1ffff7ac, 12, _uuid_regset, 'Unique Device ID'))
d.insert(soc.make_peripheral('FLASH_SIZE', 0x1ffff7cc, 2, _flash_size_regset, 'Flash Size'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 24 << 10)
def STM32F303xC_fixup(d):
d.soc_name = 'STM32F303xC'
d.cpu_info.nvicPrioBits = 4
d.cpu_info.deviceNumInterrupts = 84
# remove some core peripherals - we'll replace them in the cpu fixup
d.remove(d.NVIC)
d.remove(d.FPU)
# fix up the name of the FLASH peripheral
d.rename_peripheral('Flash', 'FLASH')
# More decode for the DBGMCU registers
f = d.DBGMCU.IDCODE.REV_ID
f.enumvals = soc.make_enumvals(f, _rev_id_enumset)
f = d.DBGMCU.IDCODE.DEV_ID
f.enumvals = soc.make_enumvals(f, _dev_id_enumset)
# more decode for the GPIO registers
gpio_decodes(d, ('A', 'B', 'C', 'D', 'E', 'F'), _STM32F303xC_altfunc)
# memory and misc periperhals
d.insert(soc.make_peripheral('sram', 0x20000000, 40 << 10, None, 'sram'))
d.insert(
soc.make_peripheral('ccm_sram', 0x10000000, 8 << 10, None,
'core coupled memory sram'))
d.insert(
soc.make_peripheral('flash_system', 0x1fffd800, 8 << 10, None,
'flash system memory'))
d.insert(
soc.make_peripheral('flash_main', 0x08000000, 256 << 10, None,
'flash main memory'))
d.insert(
soc.make_peripheral('flash_option', 0x1ffff800, 16, None,
'flash option memory'))
d.insert(
soc.make_peripheral('UID', 0x1ffff7ac, 12, _uuid_regset,
'Unique Device ID'))
d.insert(
soc.make_peripheral('FLASH_SIZE', 0x1ffff7cc, 2, _flash_size_regset,
'Flash Size'))
# ram buffer for flash writing
d.rambuf = mem.region('rambuf', 0x20000000 + 512, 32 << 10)