예제 #1
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def build(root):
    paramSets = root.find("param_include")
    vars = root.find("variables")
    cfg = root.find("config")
    timebase = root.find("timebase")
    graph = root.find("sst")


    if None != vars:
        processVars(vars)
    if None != paramSets:
        processParamSets(paramSets)
    if None != timebase:
        sst.setProgramOption('timebase', timebase.text.strip())
    if None != cfg:
        processConfig(cfg)
    if None != graph:
        buildGraph(graph)
예제 #2
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# Automatically generated SST Python input
import sst


#global system params
g_clockCycle  = "1ps"

# Define SST core options
sst.setProgramOption("timebase", g_clockCycle)
sst.setProgramOption("stopAtCycle", "10us")


# Define technology parameters
g_txnParams = {
    "numTxnGenReqQEntries":"""50""",
    "numTxnGenResQEntries":"""50""",
    "numTxnUnitReqQEntries":"""50""",
    "numTxnUnitResQEntries":"""50""",
    "numTxnDrvBufferQEntries":"""50""",
    "relCommandWidth":"""1""",
    "numCmdDrvBufferQEntries":"""50""",
    "readWriteRatio":"""0.5"""
}

# Define the simulation components

# txn gen
comp_txnGen0 = sst.Component("TxnGen0", "CramSim.c_TxnGenSeq")
comp_txnGen0.addParams(g_txnParams)

# txn driver
예제 #3
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import sst
from sst.pyproto import *


sst.setProgramOption("stopAtCycle", "10s")


class MyObject(PyProto):
    def __init__(self, name):
        PyProto.__init__(self, name)
        self.name = name
        self.countdown = 10

    def setActiveLink(self, link):
        self.myActiveLink = self.addLink(link, "1us", self._linkHandle)

    def _linkHandle(self, event):
        print self.name, "LinkHandle %s"%event.type
        print self.name, "LinkHandle: ", event.sst


    def construct(self):
        print self.name, "Construct()"

    def init(self, phase):
        print self.name, "init(%d)"%phase

    def setup(self):
        print self.name, "setup()"

    def finish(self):
예제 #4
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        nextAddr += 1

    # connect to chain
    wrapLink = sst.Link("p%d"%pimNum)
    wrapLink.connect((prevRtr,"port0", netLat),
                     (rtr, "port1", netLat))
    
    sst.popNamePrefix()
    return rtr
        

# "MAIN"

# Define SST core options
#sst.setProgramOption("partitioner", "self")
sst.setProgramOption("stopAtCycle", "300 us")
sst.setStatisticLoadLevel(7)   
sst.setStatisticOutput("sst.statOutputConsole")

#if needed, create the ariel component
if useAriel:
    ariel = makeAriel()

#make the CPU
cpuRtr = doCPU()

#make the PIMs
prevRtr = cpuRtr
for x in range(PIMs):
    prevRtr = doPIM(x, prevRtr)
예제 #5
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def processConfig(cfg):
    for line in cfg.text.strip().splitlines():
        var, val = line.split('=')
        sst.setProgramOption(var, processString(val)) # strip quotes
예제 #6
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# Automatically generated SST Python input
import sst

#global system params
g_clockCycle = "1ns"

# Define SST core options
sst.setProgramOption("timebase", g_clockCycle)
sst.setProgramOption("stopAtCycle", "11us")

# Define technology parameters
g_txnParams = {
    "numTxnGenReqQEntries": """50""",
    "numTxnGenResQEntries": """50""",
    "numTxnUnitReqQEntries": """50""",
    "numTxnUnitResQEntries": """50""",
    "numCmdReqQEntries": """400""",
    "numCmdResQEntries": """400""",
    "numChannelsPerDimm": """2""",
    "numRanksPerChannel": """2""",
    "numBankGroupsPerRank": """2""",
    "numBanksPerBankGroup": """2""",
    "relCommandWidth": """1""",
    "readWriteRatio": """1""",
    "boolUseReadA": """0""",
    "boolUseWriteA": """0""",
    "nRC": """55""",
    "nRRD": """4""",
    "nRRD_L": """6""",
    "nRRD_S": """4""",
    "nRCD": """16""",
# Automatically generated SST Python input
import sst
import os

# Define SST core options
sst.setProgramOption("timebase", "1ps")
sst.setProgramOption("stopAtCycle", "5s")

# Define the simulation components
comp_cpu = sst.Component("cpu", "prospero.prosperoCPU")
comp_cpu.addParams({
      	"verbose" : "0",
	"reader" : "prospero.ProsperoBinaryTraceReader",
	"readerParams.file" : "sstprospero-0-0-bin.trace"
})
comp_l1cache = sst.Component("l1cache", "memHierarchy.Cache")
comp_l1cache.addParams({
      "access_latency_cycles" : "1",
      "cache_frequency" : "2 Ghz",
      "replacement_policy" : "lru",
      "coherence_protocol" : "MESI",
      "associativity" : "8",
      "cache_line_size" : "64",
      "L1" : "1",
      "cache_size" : "64 KB"
})
comp_memory = sst.Component("memory", "memHierarchy.MemController")
comp_memory.addParams({
      "coherence_protocol" : "MESI",
      "clock" : "1GHz",
      "backend.access_time" : "1000 ns",
예제 #8
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import sst
import os

sst.setProgramOption("timebase", "1ps")

sst_root = os.getenv( "SST_ROOT" )

l2PrefetchParams = {
        "prefetcher": "cassini.NextBlockPrefetcher"
        }

ariel = sst.Component("a0", "ariel.ariel")
ariel.addParams({
        "verbose" : "0",
        "maxcorequeue" : "256",
        "maxissuepercycle" : "2",
        "pipetimeout" : "0",
        "executable" : sst_root + "/sst/elements/ariel/frontend/simple/examples/stream/stream",
        "arielmode" : "1",
        "arieltool" : sst_root + "/sst/elements/ariel/fesimple.so",
        "memorylevels" : "1",
        "defaultlevel" : "0"
        })

corecount = 1;

l1cache = sst.Component("l1cache", "memHierarchy.Cache")
l1cache.addParams({
        "cache_frequency" : "2 Ghz",
        "cache_size" : "64 KB",
        "coherence_protocol" : "MSI",
예제 #9
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memCtrlClockCycle = g_params["clockCycle"]
memCtrlClock = g_params["strControllerClockFreq"]
memSize = int(g_params["numChannels"]) * \
            int(g_params["numRanksPerChannel"]) * \
            int(g_params["numBankGroupsPerRank"]) * \
            int(g_params["numBanksPerBankGroup"]) * \
            int(g_params["numRowsPerBank"]) * \
            int(g_params["numColsPerBank"]) * \
            int(g_params["numBytesPerTransaction"])/(1024*1024*1024)

pagesize = 4096  #B
pagecount = memSize * 1024 * 1024 * 1024 / pagesize

# Define SST core options
sst.setProgramOption("timebase", "100ps")
#print StopAtCycle
if options.stopAtCycle != "0ms":
    print "stopAtCycle: " + options.stopAtCycle
    sst.setProgramOption("stopAtCycle", options.stopAtCycle)

## Flags
memDebug = 1
memDebugLevel = 1

## Application Info
os.environ['SIM_DESC'] = 'EIGHT_CORES'
os.environ['OMP_NUM_THREADS'] = str(coreCount)
sst_root = os.getenv("SST_ROOT")

# Enable SST Statistics Outputs for this simulation
예제 #10
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# Automatically generated SST Python input
import sst
import os

# Define SST core options
sst.setProgramOption("timebase", "1ns")
sst.setProgramOption("stopAtCycle", "100000ns")

# Define the simulation components
comp_cpu0 = sst.Component("cpu0", "memHierarchy.trivialCPU")
comp_cpu0.addParams({
      "workPerCycle" : """1000""",
      "do_write" : """1""",
      "commFreq" : """100""",
      "memSize" : """0x1000"""
})
comp_c0_l1cache = sst.Component("c0.l1cache", "memHierarchy.Cache")
comp_c0_l1cache.addParams({
      "access_latency_cycles" : """2""",
      "cache_frequency" : """2 Ghz""",
      "replacement_policy" : """lru""",
      "coherence_protocol" : """MSI""",
      "associativity" : """4""",
      "cache_line_size" : """64""",
      "cache_size" : """4 KB""",
      "printStats" : """1""",
      "L1" : """1""",
      "debug" : """"""
})
comp_cpu1 = sst.Component("cpu1", "memHierarchy.trivialCPU")
comp_cpu1.addParams({
예제 #11
0
import sst

# Define SST core options
sst.setProgramOption("stopAtCycle", "10us")

# Set up senders using user subcomponents
loader0 = sst.Component("Loader0", "coreTestElement.SubComponentLoader")
loader0.addParam("clock", "1.5GHz")
loader0.enableAllStatistics()

sub0_0 = loader0.setSubComponent("mySubComp", "coreTestElement.SubCompSender",0)
sub0_0.addParam("sendCount", 15)
sub0_0.enableAllStatistics()

sub0_1 = loader0.setSubComponent("mySubComp", "coreTestElement.SubCompSender",1)
sub0_1.addParam("sendCount", 15)
sub0_1.enableAllStatistics()

# Set up receivers using user subcomponents
loader1 = sst.Component("Loader1", "coreTestElement.SubComponentLoader")
loader1.addParam("clock", "1.0GHz")

sub1_0 = loader1.setSubComponent("mySubComp", "coreTestElement.SubCompReceiver",0)
sub1_0.enableAllStatistics()

sub1_1 = loader1.setSubComponent("mySubComp", "coreTestElement.SubCompReceiver",1)
sub1_1.enableAllStatistics()

# Set up links
link0 = sst.Link("myLink0")
link0.connect((sub0_0, "sendPort", "5ns"), (sub1_0, "recvPort", "5ns"))
    return l_params


#######################################################################################################

# Command line arguments
g_config_file = "/dccstor/memsim1/pca/config/ddr4-3200-2ch.cfg"
g_overrided_list = ""

# Setup global parameters
#[g_boolUseDefaultConfig, g_config_file] = read_arguments()
[g_config_file, g_overrided_list] = read_arguments()
g_params = setup_config_params(g_config_file, g_overrided_list)

# Define SST core options
sst.setProgramOption("timebase", "1ps")
#sst.setProgramOption("stopAtCycle", "21000us")

## Flags
memDebug = 0
memDebugLevel = 0
verbose = 0

cpu_verbose = 0
controller_verbose = 0
coherenceProtocol = "MESI"
rplPolicy = "lru"
busLat = "50 ps"
#cacheFrequency = "2 Ghz"

#cpuFrequency = "100 Mhz"
예제 #13
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        doFakeDC(rtr, nextPort, nextAddr, pimNum)
        nextPort += 1
        nextAddr += 1

    # connect to chain
    wrapLink = sst.Link("p%d" % pimNum)
    wrapLink.connect((prevRtr, "port0", netLat), (rtr, "port1", netLat))

    sst.popNamePrefix()
    return rtr


# "MAIN"

# Define SST core options
sst.setProgramOption("partitioner", "self")
#sst.setProgramOption("stopAtCycle", "2000 us")

#if needed, create the ariel component
if useAriel:
    ariel = makeAriel()

#make the CPU
cpuRtr = doCPU()

#make the PIMs
prevRtr = cpuRtr
for x in range(PIMs):
    prevRtr = doPIM(x, prevRtr)

# complete the torus
예제 #14
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# scheduler simulation input file
import sst

# Define SST core options
sst.setProgramOption("run-mode", "both")
sst.setProgramOption("partitioner", "self")

# Define the simulation components
scheduler = sst.Component("myScheduler", "scheduler.schedComponent")
scheduler.addParams({
    "traceName": "test_scheduler_0003.sim",  # job trace path (required)
    "scheduler":
    "easy",  # cons, delayed, easy, elc, pqueue, prioritize. (default: pqueue)
    "machine":
    "mesh[4,5,2]",  # mesh[xdim, ydim, zdim], simple. (default: simple)
    "allocator": "energy",  # bestfit, constraint, energy, firstfit, genalg,
    # granularmbs, hybrid, mbs, mc1x1, mm, nearest,
    # octetmbs, oldmc1x1,random, simple, sortedfreelist.
    # (default: simple)
    "taskMapper": "simple",  # simple, rcb, random (default: simple)
    "FST": "none",  # none, relaxed, strict. (default: none)
    "timeperdistance":
    ".001865[.1569,0.0129]",  # communication overhead params (default: none)
    "runningTimeSeed":
    "42",  # communication overhead randomization seed (default: none)
    "dMatrixFile":
    "DMatrix4_5_2",  # heat recirculation matrix path (default: none)
    "coresPerNode": "1"  # default: 1
})

# nodes
예제 #15
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        nextPort += 1
        nextAddr += 1

    # connect to chain
    wrapLink = sst.Link("p%d"%pimNum)
    wrapLink.connect((prevRtr,"port0", netLat),
                     (rtr, "port1", netLat))
    
    sst.popNamePrefix()
    return rtr
        

# "MAIN"

# Define SST core options
sst.setProgramOption("partitioner", "self")
#sst.setProgramOption("stopAtCycle", "2000 us")

#if needed, create the ariel component
if useAriel:
    ariel = makeAriel()

#make the CPU
cpuRtr = doCPU()

#make the PIMs
prevRtr = cpuRtr
for x in range(PIMs):
    prevRtr = doPIM(x, prevRtr)

# complete the torus
예제 #16
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# scheduler simulation input file
import sst

# Define SST core options
sst.setProgramOption("run-mode", "both")

# Define the simulation components
scheduler = sst.Component("myScheduler",             "scheduler.schedComponent")
scheduler.addParams({
      "traceName" : "test_scheduler_Atlas.sim",
      "machine" : "mesh[4,3,6]",
      "coresPerNode" : "8",
      "scheduler" : "easy",
      "allocator" : "bestfit",
      "taskMapper" : "rcb",
      "timeperdistance" : ".001865[.1569,0.0129]",
      "dMatrixFile" : "none",
      "runningTimeSeed" : "42"
})

# nodes
n0 = sst.Component("n0", "scheduler.nodeComponent")
n0.addParams({
      "nodeNum" : "0",
})
n1 = sst.Component("n1", "scheduler.nodeComponent")
n1.addParams({
      "nodeNum" : "1",
})
n2 = sst.Component("n2", "scheduler.nodeComponent")
n2.addParams({
예제 #17
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        l_params[l_tokens[0]] = l_tokens[1]

    return l_params


#######################################################################################################

g_trace_file = ""
g_config_file = ""

# Setup global parameters
[g_config_file, g_overrided_list] = read_arguments()
g_params = setup_config_params(g_config_file, g_overrided_list)

# Define SST core options
sst.setProgramOption("timebase", g_params["clockCycle"])
sst.setProgramOption("stopAtCycle", g_params["stopAtCycle"])

#sst.setStatisticLoadLevel(7)
#sst.setStatisticOutput("sst.statOutputConsole")
#sst.setStatisticOutputOption("help", "help")

# Define the simulation components
# txn gen
comp_txnGen0 = sst.Component("TxnGen", "CramSim.c_TxnGen")
comp_txnGen0.addParams(g_params)
comp_txnGen0.addParams({
    "mode": "rand",
    "numTxnPerCycle": 1,
    "readWriteRatio": 0.5
})
예제 #18
0
# scheduler simulation input file
import sst

# Define SST core options
sst.setProgramOption("run-mode", "both")
sst.setProgramOption("partitioner", "self")

# Define the simulation components
scheduler = sst.Component("myScheduler", "scheduler.schedComponent")
scheduler.addParams({
      "traceName" : "test_scheduler_0003.sim", # job trace path (required)
      "scheduler" : "easy", # cons, delayed, easy, elc, pqueue, prioritize. (default: pqueue)
      "machine" : "mesh[4,5,2]", # mesh[xdim, ydim, zdim], simple. (default: simple)
      "allocator" : "energy", # bestfit, constraint, energy, firstfit, genalg,
                              # granularmbs, hybrid, mbs, mc1x1, mm, nearest,
                              # octetmbs, oldmc1x1,random, simple, sortedfreelist.
                              # (default: simple)
      "taskMapper" : "simple", # simple, rcb, random (default: simple)
      "FST" : "none", # none, relaxed, strict. (default: none)
      "timeperdistance" : ".001865[.1569,0.0129]", # communication overhead params (default: none)
      "runningTimeSeed" : "42", # communication overhead randomization seed (default: none)
      "dMatrixFile" : "DMatrix4_5_2", # heat recirculation matrix path (default: none)
      "coresPerNode" : "1" # default: 1
})

# nodes
n0 = sst.Component("n0", "scheduler.nodeComponent")                    
n0.addParams({                                                         
        "nodeNum" : "0",                                               
})                                                                     
n1 = sst.Component("n1", "scheduler.nodeComponent")                    
예제 #19
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import sst

# Define SST core options
sst.setProgramOption("timebase", "1ps")
sst.setProgramOption("stopAtCycle", "0 ns")

# Tell SST what statistics handling we want
sst.setStatisticLoadLevel(4)

memory_mb = 128

# Define the simulation components
comp_cpu = sst.Component("cpu", "miranda.BaseCPU")
comp_cpu.addParams({
    "verbose": 0,
})
cpugen = comp_cpu.setSubComponent("generator", "miranda.GUPSGenerator")
cpugen.addParams({
    "verbose": 0,
    "count": 10000,
    "max_address": ((memory_mb) / 2) * 1024 * 1024,
})

# Enable statistics outputs
comp_cpu.enableAllStatistics({"type": "sst.AccumulatorStatistic"})

comp_l1cache = sst.Component("l1cache", "memHierarchy.Cache")
comp_l1cache.addParams({
    "access_latency_cycles": "2",
    "cache_frequency": "2 Ghz",
    "replacement_policy": "lru",
예제 #20
0
[g_config_file_list, g_overrided_list] = read_arguments()
g_params = setup_config_params(g_config_file_list, g_overrided_list)
if "dumpConfig" in g_params and int(g_params["dumpConfig"]):
        print "\n###########################\nDumping global config parameters:"
        for key in g_params:
                print key + " " + g_params[key]
        print "###########################\n"

numChannels = int(g_params["numChannels"])
maxOutstandingReqs = numChannels*64
numTxnPerCycle = numChannels
maxTxns = 100000 * numChannels


# Define SST core options
sst.setProgramOption("timebase", g_params["clockCycle"])
sst.setProgramOption("stopAtCycle", g_params["stopAtCycle"])
sst.setStatisticLoadLevel(7)
sst.setStatisticOutput("sst.statOutputConsole")


#########################################################################################################

## Configure transaction generator
comp_txnGen = sst.Component("TxnGen", "CramSim.c_TxnGen")
comp_txnGen.addParams(g_params)
comp_txnGen.addParams({
	"maxTxns" : maxTxns,
	"numTxnPerCycle" : numTxnPerCycle,
	"maxOutstandingReqs" : maxOutstandingReqs,
	"readWriteRatio" : 0.5
예제 #21
0
# scheduler simulation input file
import sst

# Define SST core options
sst.setProgramOption("run-mode", "both")

# Define the simulation components
scheduler = sst.Component("myScheduler",             "scheduler.schedComponent")
scheduler.addParams({
      "traceName" : "test_DetailedNetwork.sim",
      "machine" : "mesh[6,4,3]",
      "coresPerNode" : "4",
      "scheduler" : "easy",
      "allocator" : "bestfit",
      "timeperdistance" : ".001865[.1569,0.0129]",
      "dMatrixFile" : "none",
      "detailedNetworkSim" : "ON",
      "completedJobsTrace" : "emberCompleted.txt",
      "runningJobsTrace" : "emberRunning.txt"
})

# nodes
n0 = sst.Component("n0", "scheduler.nodeComponent")
n0.addParams({
      "nodeNum" : "0",
})
n1 = sst.Component("n1", "scheduler.nodeComponent")
n1.addParams({
      "nodeNum" : "1",
})
n2 = sst.Component("n2", "scheduler.nodeComponent")