def generate(self, **kargs):
# Disable floating point, so the StateTransition can enable it
sys_reg_name = "misa"
(sys_reg_val, valid) = self.readRegister(sys_reg_name)
state_transition_test_utils.assert_valid_register_value(
self, sys_reg_name, valid)
load_gpr64_seq = LoadGPR64(self.genThread)
rand_gpr_index = self.getRandomGPR(exclude="0")
load_gpr64_seq.load(rand_gpr_index, 0x0000028)
self.genInstruction(
"CSRRC#register#RISCV",
{
"rd": 0,
"rs1": rand_gpr_index,
"csr": self.getRegisterIndex(sys_reg_name),
},
)
state = self._createState()
StateTransition.transitionToState(state,
EStateTransitionOrderMode.ByPriority)
state_transition_test_utils.verify_state(self,
self._mExpectedStateData)
def _createVectorRegisterStateElements(self, aState):
expected_vec_reg_state_data = {}
vec_reg_count = RandomUtils.random32(0, 10)
vec_reg_indices = self.sample(range(0, 32), vec_reg_count)
max_reg_val_count = self.getLimitValue("MaxPhysicalVectorLen") // 64
for vec_reg_index in vec_reg_indices:
vec_reg_values = []
state_elem_reg_val_count = RandomUtils.random32(
1, max_reg_val_count)
for val_index in range(state_elem_reg_val_count):
vec_reg_values.append(RandomUtils.random64())
vec_reg_name = "v%d" % vec_reg_index
self.randomInitializeRegister(vec_reg_name)
aState.addRegisterStateElement(vec_reg_name, vec_reg_values)
for val_index in range(state_elem_reg_val_count,
max_reg_val_count):
field_name = "%s_%d" % (vec_reg_name, val_index)
(field_val, valid) = self.readRegister(vec_reg_name,
field=field_name)
utils.assert_valid_register_value(self, vec_reg_name, valid)
vec_reg_values.append(field_val)
expected_vec_reg_state_data[vec_reg_name] = vec_reg_values
return expected_vec_reg_state_data
def _createSystemRegisterStateElements(self, aState):
sys_reg_name = "mstatus"
aState.addSystemRegisterStateElementByField(sys_reg_name, "MIE", 0x0)
aState.addSystemRegisterStateElementByField(sys_reg_name, "MPRV", 0x1)
self.randomInitializeRegister(sys_reg_name)
(sys_reg_val, valid) = self.readRegister(sys_reg_name)
utils.assert_valid_register_value(self, sys_reg_name, valid)
sys_reg_val = utils.combine_register_value_with_field_value(
self, sys_reg_name, sys_reg_val, "MIE", 0x0)
sys_reg_val = utils.combine_register_value_with_field_value(
self, sys_reg_name, sys_reg_val, "MPRV", 0x1)
return {sys_reg_name: sys_reg_val}
def _createState(self):
state = State()
expected_sys_reg_state_data = []
mscratch_val = (RandomUtils.random32()
if self.getGlobalState("AppRegisterWidth") == 32 else
RandomUtils.random64())
state.addRegisterStateElement("mscratch", (mscratch_val, ))
expected_sys_reg_state_data.append(("mscratch", mscratch_val))
scause_name = "scause"
exception_code_var_val = RandomUtils.random32(0, 9)
state.addSystemRegisterStateElementByField(scause_name,
"EXCEPTION CODE_VAR",
exception_code_var_val)
self.randomInitializeRegister(scause_name)
(scause_val, valid) = self.readRegister(scause_name)
utils.assert_valid_register_value(self, scause_name, valid)
scause_val = utils.combine_register_value_with_field_value(
self,
scause_name,
scause_val,
"EXCEPTION CODE_VAR",
exception_code_var_val,
)
expected_sys_reg_state_data.append((scause_name, scause_val))
stvec_name = "stvec"
mode_val = RandomUtils.random32(0, 1)
state.addSystemRegisterStateElementByField(stvec_name, "MODE",
mode_val)
self.randomInitializeRegister(stvec_name)
(stvec_val, valid) = self.readRegister(stvec_name)
utils.assert_valid_register_value(self, stvec_name, valid)
stvec_val = utils.combine_register_value_with_field_value(
self, stvec_name, stvec_val, "MODE", mode_val)
expected_sys_reg_state_data.append((stvec_name, stvec_val))
self._mExpectedStateData[
EStateElementType.SystemRegister] = expected_sys_reg_state_data
return state
def _createState(self):
state = State()
expected_sys_reg_state_data = []
mcause_name = "mcause"
exception_code_var_val = RandomUtils.random32(0, 9)
state.addSystemRegisterStateElementByField(mcause_name,
"EXCEPTION CODE_VAR",
exception_code_var_val)
self.randomInitializeRegister(mcause_name)
(mcause_val, valid) = self.readRegister(mcause_name)
utils.assert_valid_register_value(self, mcause_name, valid)
mcause_val = utils.combine_register_value_with_field_value(
self,
mcause_name,
mcause_val,
"EXCEPTION CODE_VAR",
exception_code_var_val,
)
expected_sys_reg_state_data.append((mcause_name, mcause_val))
mtvec_name = "mtvec"
mode_val = RandomUtils.random32(0, 1)
state.addSystemRegisterStateElementByField("mtvec", "MODE", mode_val)
self.randomInitializeRegister(mtvec_name)
(mtvec_val, valid) = self.readRegister(mtvec_name)
utils.assert_valid_register_value(self, mtvec_name, valid)
mtvec_val = utils.combine_register_value_with_field_value(
self, mtvec_name, mtvec_val, "MODE", mode_val)
expected_sys_reg_state_data.append((mtvec_name, mtvec_val))
self._mExpectedStateData[
EStateElementType.SystemRegister] = expected_sys_reg_state_data
self._mExpectedStateData[
EStateElementType.GPR] = utils.add_random_gpr_state_elements(
self, state, RandomUtils.random32(0, 5))
self._mExpectedStateData[
EStateElementType.PC] = utils.add_random_pc_state_element(
self, state)
return state
def _createStateC(self):
state = State()
self._mExpectedStateData = {}
expected_sys_reg_state_data = []
fcsr_name = "fcsr"
state.addSystemRegisterStateElementByField(fcsr_name, "FRM", 1)
(fcsr_val, valid) = self.readRegister(fcsr_name)
utils.assert_valid_register_value(self, fcsr_name, valid)
fcsr_val = utils.combine_register_value_with_field_value(
self, fcsr_name, fcsr_val, "FRM", 1)
expected_fp_reg_state_data = []
for fp_reg_index in range(0, 32):
fp_reg_val = RandomUtils.random64(0, 0x3FFFFFFFFFFFFFFF)
state.addRegisterStateElement(("D%d" % fp_reg_index),
(fp_reg_val, ))
self._mExpectedStateData[
EStateElementType.
FloatingPointRegister] = expected_fp_reg_state_data
sstatus_name = "sstatus"
fs_val = RandomUtils.random32(1, 3)
state.addSystemRegisterStateElementByField(sstatus_name, "FS", fs_val)
(sstatus_val, valid) = self.readRegister(sstatus_name)
utils.assert_valid_register_value(self, sstatus_name, valid)
sstatus_val = utils.combine_register_value_with_field_value(
self, sstatus_name, sstatus_val, "FS", fs_val)
# Adjust expected value of SD bit according to architecture rules
(xs_val, valid) = self.readRegister(sstatus_name, field="XS")
utils.assert_valid_register_value(self, sstatus_name, valid)
(vs_val, valid) = self.readRegister(sstatus_name, field="VS")
utils.assert_valid_register_value(self, sstatus_name, valid)
if (fs_val == 3) or (xs_val == 3) or (vs_val == 3):
sstatus_val = utils.combine_register_value_with_field_value(
self, sstatus_name, sstatus_val, "SD", 1)
else:
sstatus_val = utils.combine_register_value_with_field_value(
self, sstatus_name, sstatus_val, "SD", 0)
expected_sys_reg_state_data.append((sstatus_name, sstatus_val))
self._mExpectedStateData[
EStateElementType.SystemRegister] = expected_sys_reg_state_data
return state
def _createFloatingPointRegisterStateElements(self, aState):
expected_fp_reg_state_data = {}
fp_reg_count = RandomUtils.random32(0, 10)
fp_reg_indices = self.sample(range(0, 32), fp_reg_count)
for fp_reg_index in fp_reg_indices:
fp_reg_name = "S%d" % fp_reg_index
fp_reg_val = RandomUtils.random32()
aState.addRegisterStateElement(fp_reg_name, (fp_reg_val, ))
containing_fp_reg_name = "D%d" % fp_reg_index
self.randomInitializeRegister(containing_fp_reg_name)
(orig_fp_reg_val,
valid) = self.readRegister(containing_fp_reg_name)
utils.assert_valid_register_value(self, containing_fp_reg_name,
valid)
combined_fp_reg_val = (orig_fp_reg_val &
(0xFFFFFFFF << 32)) | fp_reg_val
expected_fp_reg_state_data[
containing_fp_reg_name] = combined_fp_reg_val
return expected_fp_reg_state_data