def __init__(self, **kwargs):
self.inst('dout', sydpy.iseq, dtype=sydpy.bit8, dflt=0)
self.inst('pclk', sydpy.Process, self.pclk,
[sydpy.Delay(clk_period // 2)])
self.inst('p_gen', sydpy.Process, self.gen,
[sydpy.Delay(gen_period)])
self.lstn = ChangeListener(self.dout, sydsys)
def __init__(self, **kwargs):
# self.inst('ch_gen', sydpy.Channel)
# self.ch_gen <<= self.inst('din', sydpy.iseq, dtype=sydpy.bit8, dflt=0)
# self.ch_gen >>= self.inst('dout', sydpy.isig, dtype=sydpy.bit8, dflt=0)
self.inst('dout', sydpy.isig, dtype=sydpy.bit8, dflt=0) << \
self.inst('din', sydpy.iseq, dtype=sydpy.bit8, dflt=0)
self.inst('pclk', sydpy.Process, self.pclk,
[sydpy.Delay(clk_period // 4)])
self.inst('p_gen', sydpy.Process, self.gen,
[sydpy.Delay(gen_period)])
self.lstn = ChangeListener(self.dout, sydsys)
def __init__(self, **kwargs):
self.inst('dout', sydpy.isig, dtype=sydpy.bit8) << \
self.inst('din', sydpy.Itlm , dtype=sydpy.bit8)
self.inst('p_gen', sydpy.Process, self.gen,
[sydpy.Delay(gen_period)])
self.lstn = ChangeListener(self.dout, sydpy.system)
def pack(self):
while(1):
sydpy.ddic['sim'].wait(sydpy.Delay(10))
samples = []
for _ in range(self.S):
for d in self.din:
samples.append(d.bpop())
JesdPackerAlgo.pack(self, samples)
def pack(self):
while (1):
sydpy.ddic['sim'].wait(sydpy.Delay(10))
samples = []
for _ in range(self.S):
for d in self.din:
samples.append(d.bpop())
frame = []
for m_lane in self.pack_m:
f_lane = []
for m_byte in m_lane:
f_byte = sydpy.Bit(8)(0)
for i, m_bit in enumerate(m_byte.val):
if m_bit:
f_byte[i] = samples[m_bit[0]][m_bit[1]][m_bit[2]]
else:
f_byte[i] = 0
f_lane.append(f_byte)
frame.append(f_lane)
print(f_lane)
def __init__(self, **kwargs):
self.inst('ch_gen', sydpy.Channel)
self.ch_gen <<= self.inst('dout', sydpy.isig, dtype=sydpy.bit32, dflt=0)
self.inst('p_gen', sydpy.Process, self.gen, [sydpy.Delay(1)])
self.lstn = ChangeListener(self.dout)