def __init__(self, platform, cpu_type=None, mac_address=0x10e2d5000000, ip_address="192.168.100.50", **kwargs): clk_freq = int(142e6) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, integrated_main_ram_size=0x8000, integrated_rom_size=0x10000, integrated_sram_size=0x8000, csr_data_width=32, with_uart=False, **kwargs) self.submodules.crg = CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # ethernet mac/udp/ip stack self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") self.submodules.ethcore = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq, with_icmp=True) self.add_csr("ethcore") # etherbone bridge self.add_cpu_or_bridge(LiteEthEtherbone(self.ethcore.udp, 1234)) self.add_wb_master(self.cpu_or_bridge.wishbone.bus) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, period_ns(125e6)) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, period_ns(125e6)) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): clk_freq = int(100e6) SoCCore.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region( "spiflash", self.mem_map["spiflash"] | self.shadow_base, 16*1024*1024)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size']=0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size']=0x8000 clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) uart_interfaces = [RS232PHYInterface() for i in range(2)] self.submodules.uart = UART(uart_interfaces[0]) self.submodules.bridge = WishboneStreamingBridge(uart_interfaces[1], self.clk_freq) self.add_wb_master(self.bridge.wishbone) self.submodules.uart_phy = RS232PHY(platform.request("serial"), self.clk_freq, 115200) self.submodules.uart_multiplexer = RS232PHYMultiplexer(uart_interfaces, self.uart_phy) self.comb += self.uart_multiplexer.sel.eq(platform.request("user_sw", 0)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.oled = oled.OLED(platform.request("oled")) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) sdram_module = MT41K256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region( "spiflash", self.mem_map["spiflash"], 16*1024*1024) self.add_interrupt("uart")
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size'] = 0x8000 if 'integrated_main_ram_size' not in kwargs: kwargs['integrated_main_ram_size'] = 0x20000 clk_freq = int(50e6) SoCSDRAM.__init__(self, platform, clk_freq, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
def __init__(self, platform, csr_data_width=8, **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, csr_data_width=csr_data_width, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) self.add_csr("cas") bios_size = 0x8000 # sdram sdram_module = K4B2G1646F(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_csr("ddrphy") controller_settings = ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, integrated_rom_size=0x8000, integrated_sram_size=0x8000, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.leds = led.ClassicLed( Cat(platform.request("user_led", i) for i in range(4))) self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds")) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"] | self.shadow_base, 16 * 1024 * 1024) # sdram sdram_module = MT41K128M16(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) controller_settings = ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): dict_set_max(kwargs, 'integrated_rom_size', 0x8000) dict_set_max(kwargs, 'integrated_sram_size', 0x8000) sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(sys_clk_freq)) # Basic peripherals ------------------------------------------------------------------------ self.submodules.info = info.Info(platform, self.__class__.__name__) self.add_csr("info") self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq) self.add_csr("cas") # Add debug interface if the CPU has one --------------------------------------------------- if hasattr(self.cpu, "debug_bus"): self.register_mem( name="vexriscv_debug", address=0xf00f0000, interface=self.cpu.debug_bus, size=0x100) # Memory mapped SPI Flash ------------------------------------------------------------------ spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance( "STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2, endianness=self.cpu.endianness) self.add_csr("spiflash") self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size) self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size) self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size) self.add_wb_slave( self.mem_map["spiflash"], self.spiflash.bus, platform.spiflash_total_size) self.add_memory_region( "spiflash", self.mem_map["spiflash"], platform.spiflash_total_size) bios_size = 0x8000 self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
def __init__(self, platform, csr_data_width=8, **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size'] = 0x8000 clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, csr_data_width=csr_data_width, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size) bios_size = 0x8000 # sdram sdram_module = K4B2G1646F(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) controller_settings = ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings)
def add_sdcard(self): sdcard_pads = self.platform.request("sdcard") if hasattr(sdcard_pads, "rst"): self.comb += sdcard_pads.rst.eq(0) print(self.sys_clk_freq) self.submodules.sdclk = SDClockerS6(sys_clk_freq=self.sys_clk_freq, max_sd_clk_freq=50e6) self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.sdtimer = Timer() self.add_csr("sdclk") # self.add_csr("sdphy") self.add_csr("sdcore") self.add_csr("sdtimer") self.submodules.bist_generator = BISTBlockGenerator(random=True) self.submodules.bist_checker = BISTBlockChecker(random=True) self.add_csr("bist_generator") self.add_csr("bist_checker") self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] self.platform.add_period_constraint(self.sdclk.cd_sd.clk, period_ns(self.sys_clk_freq))
def __init__(self, platform, *args, **kwargs): BaseSoC.__init__(self, platform, *args, **kwargs) mode = "ycbcr422" if mode == "ycbcr422": dw = 16 elif mode == "rgb": dw = 32 else: raise SystemError("Unknown pixel mode.") pix_freq = 148.50e6 # hdmi in 0 hdmi_in0_pads = platform.request("hdmi_in") self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=512, device="xc7") self.submodules.hdmi_in0_freq = FrequencyMeter(period=self.clk_freq) self.comb += [ self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk), hdmi_in0_pads.txen.eq(1) ] self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix.clk, period_ns(1 * pix_freq)) self.platform.add_period_constraint( self.hdmi_in0.clocking.cd_pix1p25x.clk, period_ns(1.25 * pix_freq)) self.platform.add_period_constraint( self.hdmi_in0.clocking.cd_pix5x.clk, period_ns(5 * pix_freq)) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk) # hdmi out 0 hdmi_out0_pads = platform.request("hdmi_out") hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=dw, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut(platform.device, hdmi_out0_pads, hdmi_out0_dram_port, mode=mode, fifo_depth=4096) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk) self.platform.add_period_constraint( self.hdmi_out0.driver.clocking.cd_pix.clk, period_ns(1 * pix_freq)) self.platform.add_period_constraint( self.hdmi_out0.driver.clocking.cd_pix5x.clk, period_ns(5 * pix_freq)) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk) for name, value in sorted(self.platform.hdmi_infos.items()): self.add_constant(name, value)
def __init__(self, platform, *args, **kwargs): BaseSoC.__init__(self, platform, csr_data_width=32, *args, **kwargs) sys_clk_freq = int(100e6) # pcie phy self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=32 * 1024 * 1024) self.add_csr("pcie_phy") platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) # pcie endpoint self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) # pcie wishbone bridge self.submodules.pcie_bridge = LitePCIeWishboneBridge( self.pcie_endpoint, lambda a: 1, shadow_base=0x40000000) self.submodules.wb_swap = WishboneEndianSwap(self.pcie_bridge.wishbone) self.add_wb_master(self.wb_swap.wishbone) # pcie dma self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True) self.add_csr("pcie_dma0") # pcie msi self.submodules.pcie_msi = LitePCIeMSI() self.add_csr("pcie_msi") self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) self.interrupts = { "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, "PCIE_DMA0_READER": self.pcie_dma0.reader.irq } for i, (k, v) in enumerate(sorted(self.interrupts.items())): self.comb += self.pcie_msi.irqs[i].eq(v) self.add_constant(k + "_INTERRUPT", i) # hdmi in 0 hdmi_in0_pads = platform.request("hdmi_in", 0) self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq) self.add_csr("hdmi_in0_freq") self.submodules.hdmi_in0 = HDMIIn( hdmi_in0_pads, self.sdram.crossbar.get_port(mode="write"), fifo_depth=1024, device="xc7", split_mmcm=True) self.add_csr("hdmi_in0") self.add_csr("hdmi_in0_edid_mem") self.add_interrupt("hdmi_in0") self.comb += self.hdmi_in0_freq.clk.eq( self.hdmi_in0.clocking.cd_pix.clk), for clk in [ self.hdmi_in0.clocking.cd_pix.clk, self.hdmi_in0.clocking.cd_pix1p25x.clk, self.hdmi_in0.clocking.cd_pix5x.clk ]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) self.platform.add_period_constraint( platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6)) # hdmi out 0 hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True) self.submodules.hdmi_out0 = VideoOut(platform.device, platform.request("hdmi_out", 0), hdmi_out0_dram_port, "ycbcr422", fifo_depth=4096) self.add_csr("hdmi_out0") for clk in [ self.hdmi_out0.driver.clocking.cd_pix.clk, self.hdmi_out0.driver.clocking.cd_pix5x.clk ]: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk) for name, value in sorted(self.platform.hdmi_infos.items()): self.add_constant(name, value)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): if 'integrated_rom_size' not in kwargs: kwargs['integrated_rom_size'] = 0x8000 if 'integrated_sram_size' not in kwargs: kwargs['integrated_sram_size'] = 0x8000 clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) self.submodules.cas = cas.ControlAndStatus(platform, clk_freq) # self.submodules.leds = led.ClassicLed(Cat(platform.request("user_led", i) for i in range(4))) # self.submodules.rgb_leds = led.RGBLed(platform.request("rgb_leds")) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=platform.spiflash_clock_div, endianness=self.cpu.endianness) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"], 16 * 1024 * 1024) if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address) # sdram sdram_module = MT41K128M16(self.clk_freq, "1:4") self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.add_constant("READ_LEVELING_BITSLIP", 3) self.add_constant("READ_LEVELING_DELAY", 14) controller_settings = ControllerSettings(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True) self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=controller_settings)
def __init__(self, platform, spiflash="spiflash_1x", **kwargs): clk_freq = int(100e6) SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, integrated_rom_size=0x10000, integrated_sram_size=0x10000, **kwargs) self.submodules.crg = _CRG(platform) self.crg.cd_sys.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(clk_freq)) self.submodules.suart = shared_uart.SharedUART(self.clk_freq, 115200) self.suart.add_uart_pads(platform.request('serial')) self.submodules.uart = self.suart.uart # Basic peripherals self.submodules.info = info.Info(platform, self.__class__.__name__) # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) sdram_module = MT41K128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, controller_settings=ControllerSettings( with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)) # spi flash spiflash_pads = platform.request(spiflash) spiflash_pads.clk = Signal() self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0, i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) spiflash_dummy = { "spiflash_1x": 9, "spiflash_4x": 11, } self.submodules.spiflash = spi_flash.SpiFlash( spiflash_pads, dummy=spiflash_dummy[spiflash], div=2) self.add_constant("SPIFLASH_PAGE_SIZE", 256) self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000) self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus) self.add_memory_region("spiflash", self.mem_map["spiflash"], 16 * 1024 * 1024) if self.cpu_type == "vexriscv" and self.cpu_variant == "linux": size = 0x4000 self.submodules.emulator_ram = wishbone.SRAM(size) self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, size) bios_size = 0x8000 self.flash_boot_address = self.mem_map[ "spiflash"] + platform.gateware_size + bios_size self.add_interrupt("uart")