Python get_sim 예제들

예제 #1

def test_run_scripts():
    core = get_core("no_exe_script")
    backend = get_sim('icarus', core)
    backend.configure([])
    with pytest.raises(RuntimeError):
        os.environ['PATH'] = os.path.join(
            tests_dir, 'mock_commands') + ':' + os.environ['PATH']
        backend.build()

    core = get_core("exit_1_script")
    backend = get_sim('icarus', core)
    backend.configure([])
    with pytest.raises(RuntimeError):
        os.environ['PATH'] = os.path.join(
            tests_dir, 'mock_commands') + ':' + os.environ['PATH']
        backend.build()

예제 #2

파일: test_edatool.py 프로젝트: mytoys/fusesoc

import os
import shutil
import pytest

from test_common import get_core, get_sim

tests_dir = os.path.dirname(__file__)
core = get_core("wb_intercon")
backend = get_sim('icarus', core, export=True)
ref_dir = os.path.join(tests_dir, __name__)


def test_edatool():

    backend.configure([])
    for f in [
            'verilog_utils_0/verilog_utils.vh',
            'vlog_tb_utils_1.1/vlog_tap_generator.v',
            'vlog_tb_utils_1.1/vlog_tb_utils.v',
            'vlog_tb_utils_1.1/vlog_functions.v',
            'wb_intercon_1.0/dummy_icarus.v',
            'wb_intercon_1.0/bench/wb_mux_tb.v',
            'wb_intercon_1.0/bench/wb_upsizer_tb.v',
            'wb_intercon_1.0/bench/wb_intercon_tb.v',
            'wb_intercon_1.0/bench/wb_arbiter_tb.v',
            'wb_intercon_1.0/rtl/verilog/wb_data_resize.v',
            'wb_intercon_1.0/rtl/verilog/wb_mux.v',
            'wb_intercon_1.0/rtl/verilog/wb_arbiter.v',
            'wb_intercon_1.0/rtl/verilog/wb_upsizer.v',
            'verilog-arbiter_0-r1/src/arbiter.v',
            'wb_common_0/wb_common_params.v', 'wb_common_0/wb_common.v'

예제 #3

파일: test_icarus.py 프로젝트: MicroSmartHome/fusesoc

import os
import shutil
import pytest

from test_common import compare_file, get_core, get_sim, sim_params

tests_dir = os.path.dirname(__file__)
core = get_core("mor1kx-generic")
backend = get_sim('icarus', core)
ref_dir = os.path.join(tests_dir, __name__)
work_root = backend.work_root


def test_icarus_configure():

    backend.configure(sim_params)

    assert '' == compare_file(ref_dir, work_root, 'icarus.scr')


def test_icarus_build():
    os.environ['PATH'] = os.path.join(
        tests_dir, 'mock_commands') + ':' + os.environ['PATH']

    backend.build()

    assert '' == compare_file(ref_dir, work_root, 'iverilog-vpi.cmd')
    assert '' == compare_file(ref_dir, work_root, 'iverilog.cmd')


def test_icarus_run():

예제 #4

파일: test_ghdl.py 프로젝트: rowhit/fusesoc

import os
import pytest

from test_common import compare_files, get_core, get_sim, sim_params

tests_dir = os.path.dirname(__file__)
core = get_core("ghdltest")
backend = get_sim('ghdl', core)
ref_dir = os.path.join(tests_dir, __name__)
work_root = backend.work_root


def test_ghdl_configure():

    backend.configure(sim_params)

    compare_files(ref_dir, work_root, ['Makefile'])


def test_ghdl_build():

    os.environ['PATH'] = os.path.join(
        tests_dir, 'mock_commands') + ':' + os.environ['PATH']

    backend.build()
    assert os.path.isfile(os.path.join(work_root, 'pre_build_script_executed'))


def test_ghdl_run():

    os.environ['PATH'] = os.path.join(

예제 #5

파일: test_modelsim.py 프로젝트: rowhit/fusesoc

import os
import shutil
import pytest

from test_common import compare_file, get_core, get_sim, sim_params

tests_dir = os.path.dirname(__file__)
core      = get_core("mor1kx-generic")
backend   = get_sim('modelsim', core)
ref_dir   = os.path.join(tests_dir, __name__)
work_root = backend.work_root

def test_modelsim_configure():

    backend.configure(sim_params)

    assert '' == compare_file(ref_dir, work_root, 'fusesoc_build_rtl.tcl')
    assert '' == compare_file(ref_dir, work_root, 'fusesoc_main.tcl')
    assert '' == compare_file(ref_dir, work_root, 'fusesoc_run.tcl')
    assert '' == compare_file(ref_dir, work_root, 'Makefile')

def test_modelsim_run():

    #FIXME: Do something about the path to vsim
    os.environ['MODEL_TECH'] = os.path.join(tests_dir, 'mock_commands')
    backend.run(sim_params)

    assert '' == compare_file(ref_dir, work_root, 'run.cmd')

예제 #6

파일: test_verilator.py 프로젝트: praveenmunagapati/fusesoc

import difflib
import os
import shutil
import pytest

from fusesoc.config import Config
from fusesoc.core import Core
from fusesoc.coremanager import CoreManager

from test_common import cmdlineargs, compare_file, get_core, get_sim, vlogdefines, vlogparams

params = vlogparams + vlogdefines + cmdlineargs
tests_dir = os.path.dirname(__file__)
core = get_core("mor1kx-generic")
backend = get_sim('verilator', core)
ref_dir = os.path.join(tests_dir, __name__)
work_root = backend.work_root


def test_verilator_configure():
    backend.configure(params)

    assert '' == compare_file(ref_dir, work_root, 'config.mk')
    assert '' == compare_file(ref_dir, work_root, 'Makefile')
    assert '' == compare_file(ref_dir, work_root, core.sanitized_name + '.vc')


def test_verilator_run():
    dummy_exe = 'V' + core.verilator.top_module
    shutil.copy(os.path.join(ref_dir, dummy_exe),
                os.path.join(work_root, dummy_exe))

예제 #7

파일: test_rivierapro.py 프로젝트: rowhit/fusesoc

import os
import shutil
import pytest

from test_common import compare_file, get_core, get_sim, sim_params

tests_dir = os.path.dirname(__file__)
core = get_core("mor1kx-generic")
backend = get_sim('rivierapro', core)
#backend.toplevel = backend.system.simulator['toplevel']
ref_dir = os.path.join(tests_dir, __name__)
work_root = backend.work_root


def test_rivierapro_configure():

    backend.configure(sim_params)

    for f in [
            'fusesoc_build_rtl.tcl', 'fusesoc_build_vpi.tcl',
            'fusesoc_launch.tcl', 'fusesoc_main.tcl', 'fusesoc_run.tcl'
    ]:
        with open(os.path.join(ref_dir,
                               f)) as fref, open(os.path.join(work_root,
                                                              f)) as fgen:
            assert fref.read() == fgen.read(), f

예제 #8

import os
import pytest

from test_common import compare_files, get_core, get_sim, sim_params

tests_dir = os.path.dirname(__file__)
core = get_core("mor1kx-generic")
backend = get_sim('xsim', core)
ref_dir = os.path.join(tests_dir, __name__)
work_root = backend.work_root


def test_xsim_configure():

    backend.configure(sim_params)

    compare_files(ref_dir, work_root, [
        'config.mk', 'Makefile', core.sanitized_name + '.prj', 'run-gui.tcl',
        'run.tcl'
    ])


def test_xsim_build():
    import subprocess
    os.environ['PATH'] = os.path.join(
        tests_dir, 'mock_commands') + ':' + os.environ['PATH']

    backend.build()
    assert os.path.isfile(os.path.join(work_root, 'pre_build_script_executed'))