def run_with_lag(n, read_lag, write_lag):
data = list(range(n))
# head ptr of a
sess = verilog.session([verilog.find_file("test_cache_reg.v")])
rst = sess.main.rst
in_data = sess.main.in_data
in_valid = sess.main.in_valid
in_ready = sess.main.in_ready
out_data = sess.main.out_data
out_valid = sess.main.out_valid
out_ready = sess.main.out_ready
# hook up reader
reader = FIFODelayedReader(out_data, out_valid, out_ready, read_lag)
writer = FIFODelayedWriter(in_data, in_valid, in_ready, data, write_lag)
rst.put_int(1)
sess.yield_until_next_cycle()
rst.put_int(0)
sess.yield_until_next_cycle()
sess.yield_callbacks.append(reader)
sess.yield_callbacks.append(writer)
timeout = sum(read_lag) + sum(write_lag) + n + 10
for t in range(timeout):
sess.yield_until_next_cycle()
if len(reader.data) == n:
break
assert tuple(reader.data) == tuple(range(n))
assert len(writer.data) == 0
sess.shutdown()
def run_with_lag(n, read_lag, write_lag):
data = list(range(n))
# head ptr of a
sess = verilog.session([
verilog.find_file("test_cache_reg.v")
])
rst = sess.main.rst
in_data = sess.main.in_data
in_valid = sess.main.in_valid
in_ready = sess.main.in_ready
out_data = sess.main.out_data
out_valid = sess.main.out_valid
out_ready = sess.main.out_ready
# hook up reader
reader = FIFODelayedReader(out_data, out_valid, out_ready, read_lag)
writer = FIFODelayedWriter(in_data, in_valid, in_ready, data, write_lag)
rst.put_int(1)
sess.yield_until_next_cycle()
rst.put_int(0)
sess.yield_until_next_cycle()
sess.yield_callbacks.append(reader)
sess.yield_callbacks.append(writer)
timeout = sum(read_lag) + sum(write_lag) + n + 10
for t in range(timeout):
sess.yield_until_next_cycle()
if len(reader.data) == n:
break
assert tuple(reader.data) == tuple(range(n))
assert len(writer.data) == 0
sess.shutdown()
def test_ram_write():
n = 10
# read from offset
offset = 2
# context for VPI RAM
ctx = tvm.vpi(0)
a_np = np.zeros(n).astype('int8')
a = tvm.nd.array(a_np, ctx)
w_data = list(range(2, n))
r_data = np.array(w_data, dtype='int8')
# head ptr of a
a_ptr = int(a.handle[0].data)
sess = verilog.session([
verilog.find_file("test_vpi_mem_interface.v"),
verilog.find_file("tvm_vpi_mem_interface.v")
])
rst = sess.main.rst
write_data = sess.main.write_data
write_en = sess.main.write_en
write_ready = sess.main.write_data_ready
host_write_req = sess.main.write_req
host_write_addr = sess.main.write_addr
host_write_size = sess.main.write_size
rst.put_int(1)
sess.yield_until_next_cycle()
rst.put_int(0)
# hook up writeer
writer = FIFOWriter(write_data, write_en, write_ready, w_data)
sess.yield_callbacks.append(writer)
# request write
host_write_req.put_int(1)
host_write_addr.put_int(a_ptr + offset)
host_write_size.put_int(a.shape[0] - offset)
sess.yield_until_next_cycle()
host_write_req.put_int(0)
# yield until write is done
for i in range(a.shape[0] + 2):
sess.yield_until_next_cycle()
sess.shutdown()
# check if result matches
np.testing.assert_equal(a.asnumpy()[2:], r_data)
def test_ram_read():
n = 10
# context for VPI RAM
ctx = tvm.vpi(0)
a_np = np.arange(n).astype('int8')
a = tvm.nd.array(a_np, ctx)
# head ptr of a
a_ptr = int(a.handle[0].data)
sess = verilog.session([
verilog.find_file("test_vpi_mem_interface.v"),
verilog.find_file("tvm_vpi_mem_interface.v")
])
rst = sess.main.rst
read_data = sess.main.read_data
read_valid = sess.main.read_data_valid
read_en = sess.main.read_en
host_read_req = sess.main.read_req
host_read_addr = sess.main.read_addr
host_read_size = sess.main.read_size
rst.put_int(1)
sess.yield_until_next_cycle()
rst.put_int(0)
# hook up reader
reader = FIFOReader(read_data, read_valid)
sess.yield_callbacks.append(reader)
# request read
host_read_req.put_int(1)
host_read_addr.put_int(a_ptr)
host_read_size.put_int(a.shape[0])
sess.yield_until_next_cycle()
# second read request
host_read_addr.put_int(a_ptr + 2)
host_read_size.put_int(a.shape[0] - 2)
sess.yield_until_next_cycle()
host_read_req.put_int(0)
read_en.put_int(1)
# yield until read is done
for i in range(a.shape[0] * 3):
sess.yield_until_next_cycle()
sess.shutdown()
# check if result matches
r = np.concatenate((a_np, a_np[2:]))
np.testing.assert_equal(np.array(reader.data), r)
def test_ram_write():
n = 10
# read from offset
offset = 2
# context for VPI RAM
ctx = tvm.vpi(0)
a_np = np.zeros(n).astype('int8')
a = tvm.nd.array(a_np, ctx)
w_data = list(range(2, n))
r_data = np.array(w_data, dtype='int8')
# head ptr of a
a_ptr = int(a.handle[0].data)
sess = verilog.session([
verilog.find_file("test_vpi_mem_interface.v"),
verilog.find_file("tvm_vpi_mem_interface.v")
])
rst = sess.main.rst
write_data = sess.main.write_data
write_en = sess.main.write_en
write_ready = sess.main.write_data_ready
host_write_req = sess.main.write_req
host_write_addr = sess.main.write_addr
host_write_size = sess.main.write_size
rst.put_int(1)
sess.yield_until_next_cycle()
rst.put_int(0)
# hook up writeer
writer = FIFOWriter(write_data, write_en, write_ready, w_data)
sess.yield_callbacks.append(writer)
# request write
host_write_req.put_int(1)
host_write_addr.put_int(a_ptr + offset)
host_write_size.put_int(a.shape[0] - offset)
sess.yield_until_next_cycle()
host_write_req.put_int(0)
# yield until write is done
for i in range(a.shape[0]+2):
sess.yield_until_next_cycle()
sess.shutdown()
# check if result matches
np.testing.assert_equal(a.asnumpy()[2:], r_data)
def test_ram_read():
n = 10
# context for VPI RAM
ctx = tvm.vpi(0)
a_np = np.arange(n).astype('int8')
a = tvm.nd.array(a_np, ctx)
# head ptr of a
a_ptr = int(a.handle[0].data)
sess = verilog.session([
verilog.find_file("test_vpi_mem_interface.v"),
verilog.find_file("tvm_vpi_mem_interface.v")
])
rst = sess.main.rst
read_data = sess.main.read_data
read_valid = sess.main.read_data_valid
read_en = sess.main.read_en
host_read_req = sess.main.read_req
host_read_addr = sess.main.read_addr
host_read_size = sess.main.read_size
rst.put_int(1)
sess.yield_until_next_cycle()
rst.put_int(0)
# hook up reader
reader = FIFOReader(read_data, read_valid)
sess.yield_callbacks.append(reader)
# request read
host_read_req.put_int(1)
host_read_addr.put_int(a_ptr)
host_read_size.put_int(a.shape[0])
sess.yield_until_next_cycle()
# second read request
host_read_addr.put_int(a_ptr + 2)
host_read_size.put_int(a.shape[0] - 2)
sess.yield_until_next_cycle()
host_read_req.put_int(0)
read_en.put_int(1)
# yield until read is done
for i in range(a.shape[0] * 3):
sess.yield_until_next_cycle()
sess.shutdown()
# check if result matches
r = np.concatenate((a_np, a_np[2:]))
np.testing.assert_equal(np.array(reader.data), r)
def test_scratch():
sess = verilog.session([
verilog.find_file("test_counter.v"),
verilog.find_file("example_counter.v")
])
# Get the handles by their names
rst = sess.main.rst
counter = sess.main.counter
rst.put_int(1)
# This will advance the cycle to next pos-edge of clk.
sess.yield_until_next_cycle()
rst.put_int(0)
temp = 0
for i in range(10):
if rst.get_int():
rst.put_int(0)
temp = counter.get_int()
elif counter.get_int() == 3:
rst.put_int(1)
print("counter=%d, temp=%d" % (counter.get_int(), temp))
sess.yield_until_next_cycle()
def test_scratch():
sess = verilog.session([
verilog.find_file("test_counter.v"),
verilog.find_file("example_counter.v")
])
# Get the handles by their names
rst = sess.main.rst
counter = sess.main.counter
rst.put_int(1)
# This will advance the cycle to next pos-edge of clk.
sess.yield_until_next_cycle()
rst.put_int(0)
temp = 0
for i in range(10):
if rst.get_int():
rst.put_int(0)
temp = counter.get_int()
elif counter.get_int() == 3:
rst.put_int(1)
print("counter=%d, temp=%d" % (counter.get_int(), temp))
sess.yield_until_next_cycle()
def test_counter():
# Start a new session by run simulation on test_counter.v
# Find file will search root/verilog and root/tests/verilog
sess = verilog.session([
verilog.find_file("test_counter.v"),
verilog.find_file("example_counter.v")
])
# Get the handles by their names
rst = sess.main.rst
counter = sess.main.counter
cnt = sess.main["counter_unit1"]
assert(counter.name == "main.counter")
assert(counter.size == 4)
rst.put_int(1)
# This will advance the cycle to next pos-edge of clk.
sess.yield_until_next_cycle()
rst.put_int(0)
sess.yield_until_next_cycle()
for i in range(10):
# get value of counter.
assert(counter.get_int() == i)
sess.yield_until_next_cycle()
def test_counter():
# Start a new session by run simulation on test_counter.v
# Find file will search root/verilog and root/tests/verilog
sess = verilog.session([
verilog.find_file("test_counter.v"),
verilog.find_file("example_counter.v")
])
# Get the handles by their names
rst = sess.main.rst
counter = sess.main.counter
cnt = sess.main["counter_unit1"]
assert (counter.name == "main.counter")
assert (counter.size == 4)
rst.put_int(1)
# This will advance the cycle to next pos-edge of clk.
sess.yield_until_next_cycle()
rst.put_int(0)
sess.yield_until_next_cycle()
for i in range(10):
# get value of counter.
assert (counter.get_int() == i)
sess.yield_until_next_cycle()
def test_loop():
sess = verilog.session([
verilog.find_file("test_loop.v")
])
# Get the handles by their names
rst = sess.main.rst
iter0 = sess.main.iter0
iter1 = sess.main.iter1
ready = sess.main.ready
rst.put_int(1)
ready.put_int(1)
# This will advance the cycle to next pos-edge of clk.
sess.yield_until_next_cycle()
rst.put_int(0)
sess.yield_until_next_cycle()
for k in range(0, 1):
for i in range(0, 3):
for j in range(0, 4):
assert(iter1.get_int() == i)
assert(iter0.get_int() == j)
sess.yield_until_next_cycle()
def test_buffer_linebuff():
# Test the tvm_buffer.v module as a line buffer
# Window is 8x8, kernel is 3x3
window_width = 8
kernel_width = 3
# Find file will search root/verilog and root/tests/verilog
sess = verilog.session([
verilog.find_file("test_buffer_linebuff.v"),
verilog.find_file("tvm_buffer.v")
])
# Get the handles by their names
rst = sess.main.rst
write_advance = sess.main.write_advance
write_valid = sess.main.write_valid
write_ready = sess.main.write_ready
write_data = sess.main.write_data
read_data = sess.main.read_data
read_data_valid = sess.main.read_data_valid
# Simulation input data
test_data = np.arange(window_width*window_width).astype('int8')
# Initial state
rst.put_int(1)
write_advance.put_int(0)
write_valid.put_int(0)
write_data.put_int(0)
# De-assert reset
sess.yield_until_next_cycle()
rst.put_int(0)
# Leave the following signals set to true
sess.yield_until_next_cycle()
write_advance.put_int(1)
write_valid.put_int(1)
# Main simulation loop
write_idx = 0
read_idx = 0
while read_idx < (window_width-kernel_width+1)*(window_width-kernel_width+1)*kernel_width*kernel_width:
# write logic
if (write_idx < len(test_data)):
if (write_ready.get_int()):
write_data.put_int(int(test_data[write_idx]))
write_idx += 1
else:
write_advance.put_int(0)
write_valid.put_int(0)
# correctness checks
if (read_data_valid.get_int()):
# Derive convolution window indices
baseIdx = read_idx // (kernel_width*kernel_width)
offsetIdx = read_idx % (kernel_width*kernel_width)
yOffset = offsetIdx // kernel_width
xOffset = offsetIdx%kernel_width
pixIndex = baseIdx + yOffset * window_width + xOffset
assert(read_data.get_int()==test_data[pixIndex])
# print "{} {}".format(read_data.get_int(), test_data[pixIndex])
read_idx += 1
# step
sess.yield_until_next_cycle()
def test_buffer_doublebuff():
# Test the tvm_buffer.v module as a double buffer
# Window size is 16, buffer size is 32
window_width = 16
set_size = 8
# Find file will search root/verilog and root/tests/verilog
sess = verilog.session([
verilog.find_file("test_buffer_doublebuff.v"),
verilog.find_file("tvm_buffer.v")
])
# Get the handles by their names
rst = sess.main.rst
write_advance = sess.main.write_advance
write_addr = sess.main.write_addr
write_valid = sess.main.write_valid
write_ready = sess.main.write_ready
write_data = sess.main.write_data
read_data = sess.main.read_data
read_data_valid = sess.main.read_data_valid
# Simulation input data
test_data = np.arange(window_width*set_size).astype('int8')
# Initial state
rst.put_int(1)
write_advance.put_int(0)
write_addr.put_int(0)
write_valid.put_int(0)
write_data.put_int(0)
# De-assert reset
sess.yield_until_next_cycle()
rst.put_int(0)
# Leave the following signals set to true
sess.yield_until_next_cycle()
write_valid.put_int(1)
# Main simulation loop
write_idx = 0
read_idx = 0
while read_idx < len(test_data):
# write logic
if (write_idx < len(test_data)):
write_advance.put_int(0)
if (write_ready.get_int()):
write_data.put_int(int(test_data[write_idx]))
write_addr.put_int(write_idx % window_width)
if (write_idx%window_width==window_width-1):
write_advance.put_int(1)
write_idx += 1
else:
write_advance.put_int(0)
write_valid.put_int(0)
# correctness checks
if (read_data_valid.get_int()):
assert(read_data.get_int()==test_data[read_idx])
# print "{} {}".format(read_data.get_int(), test_data[read_idx])
read_idx += 1
# step
sess.yield_until_next_cycle()
def test_buffer_linebuff():
# Test the tvm_buffer.v module as a line buffer
# Window is 8x8, kernel is 3x3
window_width = 8
kernel_width = 3
# Find file will search root/verilog and root/tests/verilog
sess = verilog.session([
verilog.find_file("test_buffer_linebuff.v"),
verilog.find_file("tvm_buffer.v")
])
# Get the handles by their names
rst = sess.main.rst
write_advance = sess.main.write_advance
write_valid = sess.main.write_valid
write_ready = sess.main.write_ready
write_data = sess.main.write_data
read_data = sess.main.read_data
read_data_valid = sess.main.read_data_valid
# Simulation input data
test_data = np.arange(window_width * window_width).astype('int8')
# Initial state
rst.put_int(1)
write_advance.put_int(0)
write_valid.put_int(0)
write_data.put_int(0)
# De-assert reset
sess.yield_until_next_cycle()
rst.put_int(0)
# Leave the following signals set to true
sess.yield_until_next_cycle()
write_advance.put_int(1)
write_valid.put_int(1)
# Main simulation loop
write_idx = 0
read_idx = 0
while read_idx < (window_width - kernel_width + 1) * (
window_width - kernel_width + 1) * kernel_width * kernel_width:
# write logic
if (write_idx < len(test_data)):
if (write_ready.get_int()):
write_data.put_int(int(test_data[write_idx]))
write_idx += 1
else:
write_advance.put_int(0)
write_valid.put_int(0)
# correctness checks
if (read_data_valid.get_int()):
# Derive convolution window indices
baseIdx = read_idx // (kernel_width * kernel_width)
offsetIdx = read_idx % (kernel_width * kernel_width)
yOffset = offsetIdx // kernel_width
xOffset = offsetIdx % kernel_width
pixIndex = baseIdx + yOffset * window_width + xOffset
assert (read_data.get_int() == test_data[pixIndex])
# print "{} {}".format(read_data.get_int(), test_data[pixIndex])
read_idx += 1
# step
sess.yield_until_next_cycle()
def test_buffer_doublebuff():
# Test the tvm_buffer.v module as a double buffer
# Window size is 16, buffer size is 32
window_width = 16
set_size = 8
# Find file will search root/verilog and root/tests/verilog
sess = verilog.session([
verilog.find_file("test_buffer_doublebuff.v"),
verilog.find_file("tvm_buffer.v")
])
# Get the handles by their names
rst = sess.main.rst
write_advance = sess.main.write_advance
write_addr = sess.main.write_addr
write_valid = sess.main.write_valid
write_ready = sess.main.write_ready
write_data = sess.main.write_data
read_data = sess.main.read_data
read_data_valid = sess.main.read_data_valid
# Simulation input data
test_data = np.arange(window_width * set_size).astype('int8')
# Initial state
rst.put_int(1)
write_advance.put_int(0)
write_addr.put_int(0)
write_valid.put_int(0)
write_data.put_int(0)
# De-assert reset
sess.yield_until_next_cycle()
rst.put_int(0)
# Leave the following signals set to true
sess.yield_until_next_cycle()
write_valid.put_int(1)
# Main simulation loop
write_idx = 0
read_idx = 0
while read_idx < len(test_data):
# write logic
if (write_idx < len(test_data)):
write_advance.put_int(0)
if (write_ready.get_int()):
write_data.put_int(int(test_data[write_idx]))
write_addr.put_int(write_idx % window_width)
if (write_idx % window_width == window_width - 1):
write_advance.put_int(1)
write_idx += 1
else:
write_advance.put_int(0)
write_valid.put_int(0)
# correctness checks
if (read_data_valid.get_int()):
assert (read_data.get_int() == test_data[read_idx])
# print "{} {}".format(read_data.get_int(), test_data[read_idx])
read_idx += 1
# step
sess.yield_until_next_cycle()