def init_pru(self): ''' creates interface for pruss and irq ''' self.IRQ = 2 self.pruss = Icss('/dev/uio/pruss/module') self.irq = Uio("/dev/uio/pruss/irq%d" % self.IRQ, blocking=False) self.pruss.initialize(fill_memories=True)
def qep(self): if not self._qep: self.regs.clkreq.qep = 1 if self.regs.clkack.qep != 1: raise RuntimeError("submodule clock failure?") uio = Uio(self.path.parent / 'qep', parent=self) self._qep = uio.map(EQep) self._qep.irq.uio = uio return self._qep
def cap(self): if not self._cap: self.regs.clkreq.cap = 1 if self.regs.clkack.cap != 1: raise RuntimeError("submodule clock failure?") uio = Uio(self.path.parent / 'cap', parent=self) self._cap = uio.map(ECap) self._cap.irq.uio = uio return self._cap
def _add_submodule(self, name, Module, offset): module = None path = self.path / name if path.exists(): uio = Uio(path, parent=self) assert uio.region().address == self.region().address + offset module = uio.map(Module) module._uio = uio module.irq.uio = uio setattr(self, name, module) if module is None: # fallback, mainly for debugging: module = self.map(Module, offset) setattr(self, '_' + name, module)
#!/usr/bin/python3 from uio.ti.icss import Icss from uio.device import Uio import ctypes import asyncio loop = asyncio.get_event_loop() EVENT0 = 16 # range 16..31 EVENT1 = 17 # range 16..31 IRQ = 2 # range 2..9 pruss = Icss("/dev/uio/pruss/module") irq = Uio("/dev/uio/pruss/irq%d" % IRQ) intc = pruss.intc (core0, core1) = pruss.cores pruss.initialize() # clear and enable events and route them to our irq for event in EVENT0, EVENT1: intc.ev_ch[event] = IRQ intc.ev_clear_one(event) intc.ev_enable_one(event) # load program onto both cores core0.load('fw/intc-test.bin') core1.load('fw/intc-test.bin')
if TOTAL_LINES <= QUEUE_LEN: raise Exception("Less than {} lines!".format(QUEUE_LEN)) # DATA to send before PRU start data = [ERRORS.inv['ERROR_NONE']] + [0]*4 data += ([COMMANDS.inv['CMD_SCAN_DATA']] + LINE)* QUEUE_LEN # ENABLE polygon motor polygon_enable = "P9_23" GPIO.setup(polygon_enable, GPIO.OUT) GPIO.output(polygon_enable, GPIO.LOW) pruss = Icss("/dev/uio/pruss/module") irq = Uio("/dev/uio/pruss/irq%d" % IRQ, blocking=False) pruss.initialize() pruss.intc.ev_ch[PRU0_ARM_INTERRUPT] = IRQ pruss.intc.ev_clear_one(PRU0_ARM_INTERRUPT) pruss.intc.ev_enable_one(PRU0_ARM_INTERRUPT) pruss.core0.load('./determinefacettime.bin') pruss.core0.dram.write(data) pruss.core0.run() print("running core and uploaded data") byte = START_RINGBUFFER # increased scanline size each loop response = 1 # you read through ring buffer, it is extended by one to read out hsync time
#!/usr/bin/python3 import asyncio from uio.device import Uio loop = asyncio.get_event_loop() pin = Uio("/dev/uio/gpio-irq", blocking=False) pin.irq_enable() def irq_callback(): pin.irq_recv() print("Ping!") # If the irq is level-triggered instead of edge-triggered, you should # ensure that it is no longer asserted before reenabling it, otherwise # it will just immediately trigger again. pin.irq_enable() loop.add_reader(pin.fileno(), irq_callback) loop.run_forever()
#!/usr/bin/python3 from uio.device import Uio pin = Uio("/dev/uio/gpio-irq") pin.irq_enable() while True: pin.irq_recv() print("Ping!") # If the irq is level-triggered instead of edge-triggered, you should # ensure that it is no longer asserted before reenabling it, otherwise # it will just immediately trigger again. pin.irq_enable()
GPIO.output(y_direction_output, GPIO.LOW) y_enable_output = "P9_12" GPIO.setup(y_enable_output, GPIO.OUT) if ENABLED: GPIO.output(y_enable_output, GPIO.LOW) # motor on else: GPIO.output(y_enable_output, GPIO.HIGH) # ENABLE polygon motor polygon_enable = "P9_23" GPIO.setup(polygon_enable, GPIO.OUT) GPIO.output(polygon_enable, GPIO.LOW) pruss = Icss("/dev/uio/pruss/module") irq = Uio("/dev/uio/pruss/irq%d" % IRQ, blocking=True) pruss.initialize() pruss.intc.ev_ch[PRU0_ARM_INTERRUPT] = IRQ pruss.intc.ev_clear_one(PRU0_ARM_INTERRUPT) pruss.intc.ev_enable_one(PRU0_ARM_INTERRUPT) pruss.core0.load('./stabilizer.bin') # map and set parameters class Variables(Structure): _fields_ = [("ringbuffer_size", c_uint32), ("item_size", c_uint32), ("start_sync_after", c_uint32), ("global_time", c_uint32), ("polygon_time", c_uint32), ("wait_countdown", c_uint32),
#!/usr/bin/python3 from uio.device import Uio import ctypes from ctypes import c_uint32 as uint ########## L3 interconnect service network ##################################### # # Welcome to the most fussy register space on the SoC! # Only single word access allowed. Byte/halfword/multi-word access = bus error. l3_sn = Uio("/dev/uio/l3-sn") class ComponentID(ctypes.Structure): _fields_ = [ ("vendor", uint, 16), # 1 = Arteris ("type", uint, 16), ("hash", uint, 24), ("version", uint, 8), ] class FlagOutput(ctypes.Structure): src_t = uint # one bit per input _fields_ = [ ("enabled", src_t), #rw ("pending", src_t), #r- ]
#!/usr/bin/python3 from uio.device import Uio from uio.ti.subarctic.lcdc import Lcdc, lcdc_fck from time import sleep uio = Uio( "/dev/uio/lcdc" ) lcdc = uio.map( Lcdc ) # lcdc functional clock rate fck = lcdc_fck() print( "lcdc_fck = %f MHz" % (fck/1e6) ) # global config lcdc.clock_div = 6 # FIXME pick suitable value lcdc.pinmux = 0 # rfb # memory clock rate mck = fck / lcdc.clock_div print( "lcdc_mck = %f MHz (1 cycle = %f ns)" % (mck/1e6, 1e9/mck) ) # sanity checks if fck > 252000000: raise RuntimeError('lcdc functional clock exceeds max spec') if mck > 126000000: raise RuntimeError('lcdc memory clock exceeds max spec') elif mck > 42000000 and lcdc.pinmux == 0: raise RuntimeError('lcdc memory clock exceeds max spec for rfb mode') rfb = lcdc.rfb rfb.protocol = 4 # hd44780