def regDebug(word1, word2, word3, word4):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = 2
regs[1] = 1
regs[13:17] = littleEndian(word1)
regs[17:21] = littleEndian(word2)
regs[21:25] = littleEndian(word3)
regs[25:29] = littleEndian(word4)
return regs
def regRunSram(dev, startAddr, endAddr, loop=True, blockDelay=0, sync=249):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = (3 if loop else 4) #3: continuous, 4: single run
regs[1] = 0 #No register readback
regs[13:16] = littleEndian(startAddr, 3) #SRAM start address
regs[16:19] = littleEndian(endAddr-1 + dev.buildParams['SRAM_DELAY_LEN'] * blockDelay, 3) #SRAM end
regs[19] = blockDelay
regs[45] = sync
return regs
def regDebug(word1, word2, word3, word4):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = 2
regs[1] = 1
regs[13:17] = littleEndian(word1)
regs[17:21] = littleEndian(word2)
regs[21:25] = littleEndian(word3)
regs[25:29] = littleEndian(word4)
return regs
def regRunSram(dev, startAddr, endAddr, loop=True, blockDelay=0, sync=249):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = (3 if loop else 4) #3: continuous, 4: single run
regs[1] = 0 #No register readback
regs[13:16] = littleEndian(startAddr, 3) #SRAM start address
regs[16:19] = littleEndian(endAddr-1 + dev.buildParams['SRAM_DELAY_LEN'] * blockDelay, 3) #SRAM end
regs[19] = blockDelay
regs[45] = sync
return regs
def as_bytes(self):
"""Get a byte array representing this entry.
:return: ndarray(dtype='u1') of bytes for this entry.
:rtype: np.ndarray
"""
data = np.zeros(8, dtype='u1')
data[0:3] = littleEndian(self.from_addr, 3)
data[3:6] = littleEndian(self.to_addr, 3)
data[6:8] = self.operation.as_bytes()
return data
def regRun(reps, page, slave, delay, blockDelay=None, sync=249):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = 1 + (page << 7) # run memory in specified page
regs[1] = 3 # stream timing data
regs[13:15] = littleEndian(reps, 2)
if blockDelay is not None:
regs[19] = blockDelay # for boards running multi-block sequences
regs[43] = int(slave)
regs[44],regs[51] = littleEndian(int(delay),2) #this is weird because we added the high byte for start delay after the rest of the registers had been defined.
regs[45] = sync
return regs
def regRun(reps, page, slave, delay, blockDelay=None, sync=249):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = 1 + (page << 7) # run memory in specified page
regs[1] = 3 # stream timing data
regs[13:15] = littleEndian(reps, 2)
if blockDelay is not None:
regs[19] = blockDelay # for boards running multi-block sequences
regs[43] = int(slave)
regs[44],regs[51] = littleEndian(int(delay),2) #this is weird because we added the high byte for start delay after the rest of the registers had been defined.
regs[45] = sync
return regs
def toString(self):
"""Serialize jump table to a byte string for the FPGA"""
data = np.zeros(self.PACKET_LEN, dtype='<u1')
# Set counter values. Each one is 4 bytes
for i, c in enumerate(self.counters):
data[i * 4:(i + 1) * 4] = littleEndian(c, 4)
# Set start address
data[16:19] = littleEndian(self.start_addr, 3)
data[19:22] = littleEndian(self.start_addr, 3)
# Start op code
data[22] = 5
data[23] = 0
for i, jump in enumerate(self.jumps):
ofs = 24 + i * 8
data[ofs:ofs+8] = jump.as_bytes()
return data.tostring()
def as_bytes(self):
"""Get bytes for an END.
The op code is
xxxxxxxx xxxxx111
"""
return littleEndian(7, 2)
def regSerial(op, data):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = 0 #Start mode = no start
regs[1] = 1 #Readback = readback after 2us to allow for serial
regs[47] = op #Set serial operation mode to op
regs[48:51] = littleEndian(data, 3) #Serial data
return regs
def regSerial(op, data):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = 0 #Start mode = no start
regs[1] = 1 #Readback = readback after 2us to allow for serial
regs[47] = op #Set serial operation mode to op
regs[48:51] = littleEndian(data, 3) #Serial data
return regs
def pktWriteSram(device, derp, data):
assert 0 <= derp < device.buildParams['SRAM_WRITE_DERPS'], 'SRAM derp out of range: %d' % derp
data = np.asarray(data)
pkt = np.zeros(1026, dtype='<u1')
pkt[0:2] = littleEndian(derp, 2)
pkt[2:2+len(data)] = data
return pkt
def as_bytes(self):
"""Get bytes for a JUMP
The op code is
xxjjjjjj xxxx1101
where
jjjjjj is the jump index to set after the jump.
"""
# binary 1101 = decimal 13
val = (self.jump_index << 8) + 13
return littleEndian(val, 2)
def as_bytes(self):
"""Get bytes for a CYCLE.
The op code is
xxjjjjjj xxccx011
where
jjjjjj is the jump index to set if the cycle is not done.
cc is which counter to increment.
"""
jump_index = self.jump_index << 8
counter = self.counter << 4
op = 3
return littleEndian(jump_index + counter + op, 2)
def as_bytes(self):
"""Get bytes for an IDLE.
The op code is
dddddddd ddddddd0
where d[14..0] is the number of FPGA cycles to idle.
"""
if not (IDLE_MIN_CYCLES <= self.cycles <= IDLE_MAX_CYCLES):
raise ValueError(
"IDLE num cycles must fit in {} bits".format(
IDLE_NUM_BITS
)
)
return littleEndian(self.cycles << 1, 2)
def as_bytes(self):
"""Get bytes for a CHECK
The op code is
xxjjjjjj iiiin001
where
jjjjjj jump index to set when check is True
iiii specifies which daisychain bit to check
n selects whether we check for bit ON or OFF
"""
jump_idx = self.jump_index << 8
which_daisy_bit = self.which_daisy_bit << 4
bit_state = int(self.bit_state) << 3
op = 1
val = jump_idx + which_daisy_bit + bit_state + op
return littleEndian(val, 2)
def regAdcRun(device, mode, reps, filterFunc, filterStretchAt, filterStretchLen, demods, startDelay=0):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = mode
regs[1:3] = littleEndian(startDelay, 2) #Daisychain delay
regs[7:9] = littleEndian(reps, 2) #Number of repetitions
if len(filterFunc)<=1:
raise Exception('Filter function must be at least 2')
regs[9:11] = littleEndian(len(filterFunc)-1, 2) #Filter function end address. -1 because of zero indexing!
regs[11:13] = littleEndian(filterStretchAt, 2) #Stretch address for filter
regs[13:15] = littleEndian(filterStretchLen, 2) #Filter function stretch length
for i in range(device.buildParams['DEMOD_CHANNELS']):
if i not in demods:
continue
addr = 15 + 4*i
regs[addr:addr+2] = littleEndian(demods[i]['dPhi'], 2) #Lookup table step per sample
regs[addr+2:addr+4] = littleEndian(demods[i]['phi0'], 2) #Lookup table start address
return regs
def as_bytes(self):
"""Get bytes for a NOP.
The op code is xxxxxxxx xxxx0101
"""
return littleEndian(5, 2)
def regAdcSerial(bits):
regs = np.zeros(REG_PACKET_LEN, dtype='<u1')
regs[0] = 6
regs[3:6] = littleEndian(bits, 3)
return regs